Microchip Technology DV320032 Ficha De Dados

PIC3

2MX3

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DS6

0001185C-page



2012-20

13 M

rochip

chnology

6600 U4MODE

(1)

31:16

15:0

—

0000

—

SIDL

IREN

RTSMD

—

UEN<1:0>

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6610

U4STA

(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA FFFF

6620 U4TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6630 U4RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6640 U4BRG

(1)

31:16

—

0000

15:0

Baud Rate Generator Prescaler

0000

6800 U5MODE

(1)

31:16

15:0

—

0000

—

SIDL

IREN

RTSMD

—

UEN<1:0>

WAKE

LPBACK

ABAUD

RXINV

BRGH

PDSEL<1:0>

STSEL

0000

6810

U5STA

(1)

31:16

—

ADM_EN

ADDR<7:0>

0000

15:0

UTXISEL<1:0>

UTXINV

URXEN

UTXBRK

UTXEN

UTXBF

TRMT

URXISEL<1:0>

ADDEN

RIDLE

PERR

FERR

OERR

URXDA FFFF

6820 U5TXREG

31:16

—

0000

15:0

—

TX8

Transmit Register

0000

6830 U5RXREG

31:16

—

0000

15:0

—

RX8

Receive Register

0000

6840 U5BRG

(1)

31:16

—

0000

15:0

Baud Rate Generator Prescaler

0000

TABLE 4-7:

UART1 THROUGH UART5 REGISTER MAP (CONTINUED)

irt

l A

0_#

)

ist

t Ra

Bits

All

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 12.2 “CLR, SET, and INV Registers”

for more informa-

tion.