Freescale Semiconductor Demonstration Board for Freescale MC9S08SE8 DEMO9S08EL32AUTO DEMO9S08EL32AUTO Ficha De Dados

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interrupt service routine, this would allow nesting of interrupts (which is not recommended because it 
leads to programs that are difficult to debug and maintain).

For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H) 
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the 
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends 
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine 
does not use any instructions or auto-increment addressing modes that might change the value of H.

The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the 
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not 
asynchronous to program execution.

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the 
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that 
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume 
and the interrupt or reset event will be processed normally.

If a serial BACKGROUND command is issued to the MCU through the background debug interface while 
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where 
other serial background commands can be processed. This ensures that a host development system can still 
gain access to a target MCU even if it is in wait mode.

Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to 
minimize power consumption. In such systems, external circuitry is needed to control the time spent in 
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike 
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of 
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU 
from stop mode.

When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control 
bit has been set by a serial command through the background interface (or because the MCU was reset into 
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this 
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface 
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode 
where other serial background commands can be processed. This ensures that a host development system 
can still gain access to a target MCU even if it is in stop mode.

Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop 
mode. Refer to the 

Modes of Operation 

chapter for more details.