Manual Do Utilizador (DEMO9S08EL32AUTO)índice analíticoCAUTIONARY NOTES4TERMINOLOGY4FEATURES5REFERENCES6GETTING STARTED6MEMORY MAP6SOFTWARE DEVELOPMENT6DEVELOPMENT SUPPORT7Integrated BDM7BDM_PORT Header7POWER7POWER SELECT8PWR_SEL8VX_EN9RESET SWITCH9LOW VOLTAGE RESET9TIMING10COMMUNICATIONS10RS-23210COM Connector10LIN Communications11LIN_EN11COM_SEL11USER I/O12Switches12LED’s12Potentiometer12Temperature Sensor13User Signals13User Enable13MCU I/O PORT14Tamanho: 100 KBPáginas: 14Language: EnglishAbrir o manual
Ficha De Dados (DEMO9S08EL32AUTO)índice analíticoChapter 1 Device Overview191.1 Devices in the MC9S08EL32 Series and MC9S08SL16 Series191.2 MCU Block Diagram201.3 System Clock Distribution23Chapter 2 Pins and Connections252.1 Device Pin Assignment252.2 Recommended System Connections262.2.1 Power262.2.2 Oscillator272.2.3 RESET272.2.4 Background / Mode Select (BKGD/MS)282.2.5 General-Purpose I/O and Peripheral Ports28Chapter 3 Modes of Operation313.1 Introduction313.2 Features313.3 Run Mode313.4 Active Background Mode313.5 Wait Mode323.6 Stop Modes323.6.1 Stop3 Mode333.6.1.1 LVD Enabled in Stop Mode333.6.1.2 Active BDM Enabled in Stop Mode333.7 Stop2 Mode343.8 On-Chip Peripheral Modules in Stop Modes34Chapter 4 Memory374.1 MC9S08EL32 Series and MC9S08SL16 Series Memory Map374.2 Reset and Interrupt Vector Assignments384.3 Register Addresses and Bit Assignments394.4 RAM464.5 FLASH and EEPROM474.5.1 Features474.5.2 Program and Erase Times474.5.3 Program and Erase Command Execution484.5.4 Burst Program Execution494.5.5 Sector Erase Abort514.5.6 Access Errors524.5.7 Block Protection534.5.8 Vector Redirection534.5.9 Security534.5.10 EEPROM Mapping554.5.11 FLASH and EEPROM Registers and Control Bits554.5.11.1 FLASH and EEPROM Clock Divider Register (FCDIV)554.5.11.2 FLASH and EEPROM Options Register (FOPT and NVOPT)574.5.11.3 FLASH and EEPROM Configuration Register (FCNFG)584.5.11.4 FLASH and EEPROM Protection Register (FPROT and NVPROT)594.5.11.5 FLASH and EEPROM Status Register (FSTAT)614.5.11.6 FLASH and EEPROM Command Register (FCMD)62Chapter 5 Resets, Interrupts, and General System Control635.1 Introduction635.2 Features635.3 MCU Reset635.4 Computer Operating Properly (COP) Watchdog645.5 Interrupts655.5.1 Interrupt Stack Frame665.5.2 Interrupt Vectors, Sources, and Local Masks675.6 Low-Voltage Detect (LVD) System685.6.1 Power-On Reset Operation695.6.2 Low-Voltage Detection (LVD) Reset Operation695.6.3 Low-Voltage Warning (LVW) Interrupt Operation695.7 Reset, Interrupt, and System Control Registers and Control Bits705.7.1 System Reset Status Register (SRS)715.7.2 System Background Debug Force Reset Register (SBDFR)725.7.3 System Options Register 1 (SOPT1)735.7.4 System Options Register 2 (SOPT2)745.7.5 System Device Identification Register (SDIDH, SDIDL)755.7.6 System Power Management Status and Control 1 Register (SPMSC1)765.7.7 System Power Management Status and Control 2 Register (SPMSC2)77Chapter 6 Parallel Input/Output Control796.1 Port Data and Data Direction796.2 Pull-up, Slew Rate, and Drive Strength806.3 Pin Interrupts816.3.1 Edge Only Sensitivity816.3.2 Edge and Level Sensitivity816.3.3 Pull-up/Pull-down Resistors826.3.4 Pin Interrupt Initialization826.4 Pin Behavior in Stop Modes826.5 Parallel I/O and Pin Control Registers826.5.1 Port A Registers836.5.1.1 Port A Data Register (PTAD)836.5.1.2 Port A Data Direction Register (PTADD)836.5.1.3 Port A Pull Enable Register (PTAPE)846.5.1.4 Port A Slew Rate Enable Register (PTASE)846.5.1.5 Port A Drive Strength Selection Register (PTADS)856.5.1.6 Port A Interrupt Status and Control Register (PTASC)856.5.1.7 Port A Interrupt Pin Select Register (PTAPS)866.5.1.8 Port A Interrupt Edge Select Register (PTAES)866.5.2 Port B Registers876.5.2.1 Port B Data Register (PTBD)876.5.2.2 Port B Data Direction Register (PTBDD)876.5.2.3 Port B Pull Enable Register (PTBPE)886.5.2.4 Port B Slew Rate Enable Register (PTBSE)886.5.2.5 Port B Drive Strength Selection Register (PTBDS)896.5.2.6 Port B Interrupt Status and Control Register (PTBSC)896.5.2.7 Port B Interrupt Pin Select Register (PTBPS)906.5.2.8 Port B Interrupt Edge Select Register (PTBES)906.5.3 Port C Registers916.5.3.1 Port C Data Register (PTCD)916.5.3.2 Port C Data Direction Register (PTCDD)916.5.3.3 Port C Pull Enable Register (PTCPE)926.5.3.4 Port C Slew Rate Enable Register (PTCSE)926.5.3.5 Port C Drive Strength Selection Register (PTCDS)936.5.3.6 Port C Interrupt Status and Control Register (PTCSC)936.5.3.7 Port C Interrupt Pin Select Register (PTCPS)946.5.3.8 Port C Interrupt Edge Select Register (PTCES)94Chapter 7 Central Processor Unit (S08CPUV3)957.1 Introduction957.1.1 Features957.2 Programmer’s Model and CPU Registers967.2.1 Accumulator (A)967.2.2 Index Register (H:X)967.2.3 Stack Pointer (SP)977.2.4 Program Counter (PC)977.2.5 Condition Code Register (CCR)977.3 Addressing Modes997.3.1 Inherent Addressing Mode (INH)997.3.2 Relative Addressing Mode (REL)997.3.3 Immediate Addressing Mode (IMM)997.3.4 Direct Addressing Mode (DIR)997.3.5 Extended Addressing Mode (EXT)1007.3.6 Indexed Addressing Mode1007.3.6.1 Indexed, No Offset (IX)1007.3.6.2 Indexed, No Offset with Post Increment (IX+)1007.3.6.3 Indexed, 8-Bit Offset (IX1)1007.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)1007.3.6.5 Indexed, 16-Bit Offset (IX2)1007.3.6.6 SP-Relative, 8-Bit Offset (SP1)1007.3.6.7 SP-Relative, 16-Bit Offset (SP2)1017.4 Special Operations1017.4.1 Reset Sequence1017.4.2 Interrupt Sequence1017.4.3 Wait Mode Operation1027.4.4 Stop Mode Operation1027.4.5 BGND Instruction1037.5 HCS08 Instruction Set Summary103Chapter 8 Internal Clock Source (S08ICSV2)1158.1 Introduction1158.1.1 Module Configuration1158.1.2 Features1178.1.3 Block Diagram1178.1.4 Modes of Operation1188.1.4.1 FLL Engaged Internal (FEI)1188.1.4.2 FLL Engaged External (FEE)1188.1.4.3 FLL Bypassed Internal (FBI)1188.1.4.4 FLL Bypassed Internal Low Power (FBILP)1198.1.4.5 FLL Bypassed External (FBE)1198.1.4.6 FLL Bypassed External Low Power (FBELP)1198.1.4.7 Stop (STOP)1198.2 External Signal Description1198.3 Register Definition1198.3.1 ICS Control Register 1 (ICSC1)1208.3.2 ICS Control Register 2 (ICSC2)1218.3.3 ICS Trim Register (ICSTRM)1228.3.4 ICS Status and Control (ICSSC)1228.4 Functional Description1238.4.1 Operational Modes1238.4.1.1 FLL Engaged Internal (FEI)1238.4.1.2 FLL Engaged External (FEE)1248.4.1.3 FLL Bypassed Internal (FBI)1248.4.1.4 FLL Bypassed Internal Low Power (FBILP)1248.4.1.5 FLL Bypassed External (FBE)1258.4.1.6 FLL Bypassed External Low Power (FBELP)1258.4.1.7 Stop1258.4.2 Mode Switching1258.4.3 Bus Frequency Divider1268.4.4 Low Power Bit Usage1268.4.5 Internal Reference Clock1268.4.6 Optional External Reference Clock1268.4.7 Fixed Frequency Clock127Chapter 9 5-V Analog Comparator (S08ACMPV2)1299.1 Introduction1299.1.1 ACMPx Configuration Information1299.1.2 ACMP1/TPM1 Configuration Information1299.1.3 Features1319.1.4 Modes of Operation1319.1.4.1 ACMP in Wait Mode1319.1.4.2 ACMP in Stop Modes1319.1.4.3 ACMP in Active Background Mode1319.1.5 Block Diagram1329.2 External Signal Description1339.3 Memory Map1339.3.1 Register Descriptions1339.3.1.1 ACMPx Status and Control Register (ACMPxSC)1349.4 Functional Description135Chapter 10 Analog-to-Digital Converter (S08ADCV1)13710.1 Introduction13710.1.1 Channel Assignments13710.1.2 Alternate Clock13810.1.3 Hardware Trigger13810.1.4 Temperature Sensor13810.1.5 Features14110.1.6 Block Diagram14110.2 External Signal Description14210.2.1 Analog Power (VDDAD)14310.2.2 Analog Ground (VSSAD)14310.2.3 Voltage Reference High (VREFH)14310.2.4 Voltage Reference Low (VREFL)14310.2.5 Analog Channel Inputs (ADx)14310.3 Register Definition14310.3.1 Status and Control Register 1 (ADCSC1)14310.3.2 Status and Control Register 2 (ADCSC2)14510.3.3 Data Result High Register (ADCRH)14610.3.4 Data Result Low Register (ADCRL)14610.3.5 Compare Value High Register (ADCCVH)14710.3.6 Compare Value Low Register (ADCCVL)14710.3.7 Configuration Register (ADCCFG)14710.3.8 Pin Control 1 Register (APCTL1)14910.3.9 Pin Control 2 Register (APCTL2)15010.3.10 Pin Control 3 Register (APCTL3)15110.4 Functional Description15210.4.1 Clock Select and Divide Control15210.4.2 Input Select and Pin Control15310.4.3 Hardware Trigger15310.4.4 Conversion Control15310.4.4.1 Initiating Conversions15310.4.4.2 Completing Conversions15410.4.4.3 Aborting Conversions15410.4.4.4 Power Control15410.4.4.5 Total Conversion Time15410.4.5 Automatic Compare Function15610.4.6 MCU Wait Mode Operation15610.4.7 MCU Stop3 Mode Operation15610.4.7.1 Stop3 Mode With ADACK Disabled15610.4.7.2 Stop3 Mode With ADACK Enabled15710.4.8 MCU Stop1 and Stop2 Mode Operation15710.5 Initialization Information15710.5.1 ADC Module Initialization Example15710.5.1.1 Initialization Sequence15710.5.1.2 Pseudo - Code Example15810.6 Application Information15910.6.1 External Pins and Routing15910.6.1.1 Analog Supply Pins15910.6.1.2 Analog Reference Pins16010.6.1.3 Analog Input Pins16010.6.2 Sources of Error16110.6.2.1 Sampling Error16110.6.2.2 Pin Leakage Error16110.6.2.3 Noise-Induced Errors16110.6.2.4 Code Width and Quantization Error16210.6.2.5 Linearity Errors16210.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes162Chapter 11 Inter-Integrated Circuit (S08IICV2)16511.1 Introduction16511.1.1 Module Configuration16511.1.2 Features16711.1.3 Modes of Operation16711.1.4 Block Diagram16811.2 External Signal Description16811.2.1 SCL - Serial Clock Line16811.2.2 SDA - Serial Data Line16811.3 Register Definition16811.3.1 IIC Address Register (IICA)16911.3.2 IIC Frequency Divider Register (IICF)16911.3.3 IIC Control Register (IICC1)17211.3.4 IIC Status Register (IICS)17211.3.5 IIC Data I/O Register (IICD)17311.3.6 IIC Control Register 2 (IICC2)17411.4 Functional Description17511.4.1 IIC Protocol17511.4.1.1 Start Signal17511.4.1.2 Slave Address Transmission17611.4.1.3 Data Transfer17611.4.1.4 Stop Signal17611.4.1.5 Repeated Start Signal17711.4.1.6 Arbitration Procedure17711.4.1.7 Clock Synchronization17711.4.1.8 Handshaking17811.4.1.9 Clock Stretching17811.4.2 10-bit Address17811.4.2.1 Master-Transmitter Addresses a Slave-Receiver17811.4.2.2 Master-Receiver Addresses a Slave-Transmitter17811.4.3 General Call Address17911.5 Resets17911.6 Interrupts17911.6.1 Byte Transfer Interrupt17911.6.2 Address Detect Interrupt18011.6.3 Arbitration Lost Interrupt18011.7 Initialization/Application Information181Chapter 12 Slave LIN Interface Controller (S08SLICV1)18312.1 Introduction18312.1.1 Features18512.1.2 Modes of Operation18612.1.2.1 Power Off18612.1.2.2 Reset18612.1.2.3 SLIC Disabled18712.1.2.4 SLIC Run18712.1.2.5 SLIC Wait18712.1.2.6 Wakeup from SLIC Wait with CPU in WAIT18712.1.2.7 SLIC Stop18712.1.2.8 Normal and Emulation Mode Operation18812.1.2.9 Special Mode Operation18812.1.2.10 Low-Power Options18812.1.3 Block Diagram18912.2 External Signal Description18912.2.1 SLCTx - SLIC Transmit Pin18912.2.2 SLCRx - SLIC Receive Pin18912.3 Register Definition18912.3.1 SLIC Control Register 1 (SLCC1)18912.3.2 SLIC Control Register 2 (SLCC2)19112.3.3 SLIC Bit Time Registers (SLCBTH, SLCBTL)19312.3.4 SLIC Status Register (SLCS)19412.3.5 SLIC State Vector Register (SLCSV)19512.3.5.1 LIN Mode Operation19612.3.5.2 Byte Transfer Mode Operation19812.3.6 SLIC Data Length Code Register (SLCDLC)20012.3.7 SLIC Identifier and Data Registers (SLCID, SLCD7-SLCD0)20112.4 Functional Description20212.5 Interrupts20212.5.1 SLIC During Break Interrupts20212.6 Initialization/Application Information20212.6.1 LIN Message Frame Header20312.6.2 LIN Data Field20312.6.3 LIN Checksum Field20412.6.4 SLIC Module Constraints20412.6.5 SLCSV Interrupt Handling20412.6.6 SLIC Module Initialization Procedure20412.6.6.1 LIN Mode Initialization20412.6.6.2 Byte Transfer Mode Initialization20512.6.7 Handling LIN Message Headers20612.6.7.1 LIN Message Headers20712.6.7.2 Possible Errors on Message Headers20912.6.8 Handling Command Message Frames20912.6.8.1 Standard Command Message Frames20912.6.8.2 Extended Command Message Frames21112.6.8.3 Possible Errors on Command Message Data21212.6.9 Handling Request LIN Message Frames21212.6.9.1 Standard Request Message Frames21212.6.9.2 Extended Request Message Frames21512.6.9.3 Transmit Abort21612.6.9.4 Possible Errors on Request Message Data21612.6.10 Handling IMSG to Minimize Interrupts21612.6.11 Sleep and Wakeup Operation21712.6.12 Polling Operation21712.6.13 LIN Data Integrity Checking Methods21712.6.14 High-Speed LIN Operation21812.6.15 Bit Error Detection and Physical Layer Delay22112.6.16 Byte Transfer Mode Operation22212.6.17 Oscillator Trimming with SLIC22612.6.18 Digital Receive Filter22812.6.18.1 Digital Filter Operation22812.6.18.2 Digital Filter Performance229Chapter 13 Serial Peripheral Interface (S08SPIV3)23113.1 Introduction23113.1.1 Features23313.1.2 Block Diagrams23313.1.2.1 SPI System Block Diagram23313.1.2.2 SPI Module Block Diagram23413.1.3 SPI Baud Rate Generation23513.2 External Signal Description23613.2.1 SPSCK - SPI Serial Clock23613.2.2 MOSI - Master Data Out, Slave Data In23613.2.3 MISO - Master Data In, Slave Data Out23613.2.4 SS - Slave Select23613.3 Modes of Operation23713.3.1 SPI in Stop Modes23713.4 Register Definition23713.4.1 SPI Control Register 1 (SPIC1)23713.4.2 SPI Control Register 2 (SPIC2)23813.4.3 SPI Baud Rate Register (SPIBR)23913.4.4 SPI Status Register (SPIS)24013.4.5 SPI Data Register (SPID)24113.5 Functional Description24213.5.1 SPI Clock Formats24213.5.2 SPI Interrupts24513.5.3 Mode Fault Detection245Chapter 14 Serial Communications Interface (S08SCIV4)24714.1 Introduction24714.1.1 Features24914.1.2 Modes of Operation24914.1.3 Block Diagram25014.2 Register Definition25214.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL)25214.2.2 SCI Control Register 1 (SCIxC1)25314.2.3 SCI Control Register 2 (SCIxC2)25414.2.4 SCI Status Register 1 (SCIxS1)25514.2.5 SCI Status Register 2 (SCIxS2)25714.2.6 SCI Control Register 3 (SCIxC3)25814.2.7 SCI Data Register (SCIxD)25914.3 Functional Description25914.3.1 Baud Rate Generation25914.3.2 Transmitter Functional Description26014.3.2.1 Send Break and Queued Idle26114.3.3 Receiver Functional Description26114.3.3.1 Data Sampling Technique26214.3.3.2 Receiver Wakeup Operation26214.3.4 Interrupts and Status Flags26314.3.5 Additional SCI Functions26414.3.5.1 8- and 9-Bit Data Modes26414.3.5.2 Stop Mode Operation26514.3.5.3 Loop Mode26514.3.5.4 Single-Wire Operation265Chapter 15 Real-Time Counter (S08RTCV1)26715.1 Introduction26715.1.1 Features27015.1.2 Modes of Operation27015.1.2.1 Wait Mode27015.1.2.2 Stop Modes27015.1.2.3 Active Background Mode27015.1.3 Block Diagram27115.2 External Signal Description27115.3 Register Definition27115.3.1 RTC Status and Control Register (RTCSC)27215.3.2 RTC Counter Register (RTCCNT)27315.3.3 RTC Modulo Register (RTCMOD)27315.4 Functional Description27315.4.1 RTC Operation Example27415.5 Initialization/Application Information275Chapter 16 Timer Pulse-Width Modulator (S08TPMV2)27716.1 Introduction27716.1.1 Features27916.1.2 Modes of Operation27916.1.3 Block Diagram28016.2 Signal Description28216.2.1 Detailed Signal Descriptions28216.2.1.1 EXTCLK - External Clock Source28316.2.1.2 TPMxCHn - TPM Channel n I/O Pin(s)28316.3 Register Definition28616.3.1 TPM Status and Control Register (TPMxSC)28616.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL)28716.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL)28816.3.4 TPM Channel n Status and Control Register (TPMxCnSC)28916.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)29116.4 Functional Description29216.4.1 Counter29316.4.1.1 Counter Clock Source29316.4.1.2 Counter Overflow and Modulo Reset29416.4.1.3 Counting Modes29516.4.1.4 Manual Counter Reset29516.4.2 Channel Mode Selection29516.4.2.1 Input Capture Mode29516.4.2.2 Output Compare Mode29516.4.2.3 Edge-Aligned PWM Mode29616.4.2.4 Center-Aligned PWM Mode29716.5 Reset Overview29816.5.1 General29816.5.2 Description of Reset Operation29816.6 Interrupts29816.6.1 General29816.6.2 Description of Interrupt Operation29916.6.2.1 Timer Overflow Interrupt (TOF) Description29916.6.2.2 Channel Event Interrupt Description30016.7 The Differences from TPM v2 to TPM v3300Chapter 17 Development Support30517.1 Introduction30517.1.1 Forcing Active Background30517.1.2 Features30817.2 Background Debug Controller (BDC)30817.2.1 BKGD Pin Description30917.2.2 Communication Details31017.2.3 BDC Commands31417.2.4 BDC Hardware Breakpoint31617.3 On-Chip Debug System (DBG)31717.3.1 Comparators A and B31717.3.2 Bus Capture Information and FIFO Operation31717.3.3 Change-of-Flow Information31817.3.4 Tag vs. Force Breakpoints and Triggers31817.3.5 Trigger Modes31917.3.6 Hardware Breakpoints32117.4 Register Definition32117.4.1 BDC Registers and Control Bits32117.4.1.1 BDC Status and Control Register (BDCSCR)32217.4.1.2 BDC Breakpoint Match Register (BDCBKPT)32317.4.2 System Background Debug Force Reset Register (SBDFR)32317.4.3 DBG Registers and Control Bits32417.4.3.1 Debug Comparator A High Register (DBGCAH)32417.4.3.2 Debug Comparator A Low Register (DBGCAL)32417.4.3.3 Debug Comparator B High Register (DBGCBH)32417.4.3.4 Debug Comparator B Low Register (DBGCBL)32417.4.3.5 Debug FIFO High Register (DBGFH)32517.4.3.6 Debug FIFO Low Register (DBGFL)32517.4.3.7 Debug Control Register (DBGC)32617.4.3.8 Debug Trigger Register (DBGT)32717.4.3.9 Debug Status Register (DBGS)328Appendix A Electrical Characteristics329A.1 Introduction329A.2 Parameter Classification329A.3 Absolute Maximum Ratings329A.4 Thermal Characteristics330A.5 ESD Protection and Latch-Up Immunity331A.6 DC Characteristics332A.7 Supply Current Characteristics336A.8 External Oscillator (XOSC) Characteristics339A.9 Internal Clock Source (ICS) Characteristics340A.10 Analog Comparator (ACMP) Electricals341A.11 ADC Characteristics342A.12 AC Characteristics345A.12.1 Control Timing345A.12.2 TPM/MTIM Module Timing346A.12.3 SPI347A.13 Flash and EEPROM Specifications350A.14 EMC Performance351A.14.1 Radiated Emissions351A.14.2 Conducted Transient Susceptibility352Appendix B Ordering Information and Mechanical Drawings353B.1 Ordering Information353B.1.1 Device Numbering Scheme353B.2 Mechanical Drawings354Tamanho: 8 MBPáginas: 356Language: EnglishAbrir o manual
