Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados
Códigos do produto
TWR-S12G240
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
240
Freescale Semiconductor
2.4.3.51
Port AD Input Register (PTI0AD)
2.4.3.52
Port AD Input Register (PTI1AD)
Table 2-76. PT1AD Register Field Descriptions
Field
Description
7-0
PT1AD
Port AD general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read if the digital input buffers are enabled (
”).
Address 0x0272 (
,
)
Access: User read only
1
1
Read: Anytime
Write: Never
Write: Never
7
6
5
4
3
2
1
0
R
PTI0AD7
PTI0AD6
PTI0AD5
PTI0AD4
PTI0AD3
PTI0AD2
PTI0AD1
PTI0AD0
W
Reset
0
0
0
0
0
0
0
0
Address 0x0272 (
)
Access: User read only
7
6
5
4
3
2
1
0
R
0
0
0
0
PTI0AD3
PTI0AD2
PTI0AD1
PTI0AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-51. Port AD Input Register (PTI0AD)
Table 2-77. PTI0AD Register Field Descriptions
Field
Description
7-0
PTI0AD
Port AD input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0273
Access: User read only
1
1
Read: Anytime
Write: Never
Write: Never
7
6
5
4
3
2
1
0
R
PTI1AD7
PTI1AD6
PTI1AD5
PTI1AD4
PTI1AD3
PTI1AD2
PTI1AD1
PTI1AD0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-52. Port AD Input Register (PTI1AD)