Manuais de utilizador para Freescale Semiconductor Tower System Module S12G240 TWR-S12G240

índice analítico

• Chapter 1 Device Overview MC9S12G-Family

  37
  • 1.1 Introduction

    37
  • 1.2 Features

    38
    • 1.2.1 MC9S12G-Family Comparison

      38
    • 1.2.2 Chip-Level Features

      40
  • 1.3 Module Features

    40
    • 1.3.1 S12 16-Bit Central Processor Unit (CPU)

      41
    • 1.3.2 On-Chip Flash with ECC

      41
    • 1.3.3 On-Chip SRAM

      41
    • 1.3.4 Port Integration Module (PIM)

      41
    • 1.3.5 Main External Oscillator (XOSCLCP)

      42
    • 1.3.6 Internal RC Oscillator (IRC)

      42
    • 1.3.7 Internal Phase-Locked Loop (IPLL)

      42
    • 1.3.8 System Integrity Support

      43
    • 1.3.9 Timer (TIM)

      43
    • 1.3.10 Pulse Width Modulation Module (PWM)

      43
    • 1.3.11 Controller Area Network Module (MSCAN)

      43
    • 1.3.12 Serial Communication Interface Module (SCI)

      44
    • 1.3.13 Serial Peripheral Interface Module (SPI)

      44
    • 1.3.14 Analog-to-Digital Converter Module (ADC)

      44
    • 1.3.15 Reference Voltage Attenuator (RVA)

      45
    • 1.3.16 Digital-to-Analog Converter Module (DAC)

      45
    • 1.3.17 Analog Comparator (ACMP)

      45
    • 1.3.18 On-Chip Voltage Regulator (VREG)

      45
    • 1.3.19 Background Debug (BDM)

      45
    • 1.3.20 Debugger (DBG)

      45
  • 1.4 Key Performance Parameters

    46
  • 1.5 Block Diagram

    46
  • 1.6 Family Memory Map

    47
    • 1.6.1 Part ID Assignments

      52
  • 1.7 Signal Description and Device Pinouts

    52
    • 1.7.1 Pin Assignment Overview

      53
    • 1.7.2 Detailed Signal Descriptions

      53
      • 1.7.2.1 RESET - External Reset Signal

        53
      • 1.7.2.2 TEST - Test Pin

        53
      • 1.7.2.3 BKGD / MODC - Background Debug and Mode Pin

        54
      • 1.7.2.4 EXTAL, XTAL - Oscillator Signal

        54
      • 1.7.2.5 PAD[15:0] / KWAD[15:0] - Port AD Input Pins of ADC

        54
      • 1.7.2.6 PA[7:0] - Port A I/O Signals

        54
      • 1.7.2.7 PB[7:0] - Port B I/O Signals

        54
      • 1.7.2.8 PC[7:0] - Port C I/O Signals

        54
      • 1.7.2.9 PD[7:0] - Port D I/O Signals

        54
      • 1.7.2.10 PE[1:0] - Port E I/O Signals

        54
      • 1.7.2.11 PJ[7:0] / KWJ[7:0] - Port J I/O Signals

        55
      • 1.7.2.12 PM[3:0] - Port M I/O Signals

        55
      • 1.7.2.13 PP[7:0] / KWP[7:0] - Port P I/O Signals

        55
      • 1.7.2.14 PS[7:0] - Port S I/O Signals

        55
      • 1.7.2.15 PT[7:0] - Port TI/O Signals

        55
      • 1.7.2.16 AN[15:0] - ADC Input Signals

        55
      • 1.7.2.17 ACMP Signals

        55
      • 1.7.2.18 DAC Signals

        56
      • 1.7.2.19 SPI Signals

        56
      • 1.7.2.20 SCI Signals

        56
      • 1.7.2.21 CAN signals

        57
      • 1.7.2.22 PWM[7:0] Signals

        57
      • 1.7.2.23 Internal Clock outputs

        57
      • 1.7.2.24 IOC[7:0] Signals

        57
      • 1.7.2.25 IRQ

        58
      • 1.7.2.26 XIRQ

        58
      • 1.7.2.27 ETRIG[3:0]

        58
    • 1.7.3 Power Supply Pins

      58
      • 1.7.3.1 VDDX[3:1]/VDDX, VSSX[3:1]/VSSX- Power and Ground Pins for I/O Drivers

        58
      • 1.7.3.2 VDDR - Power Pin for Internal Voltage Regulator

        58
      • 1.7.3.3 VSS - Core Ground Pin

        58
      • 1.7.3.4 VDDA, VSSA - Power Supply Pins for DAC,ACMP, RVA, ADC and Voltage Regulator

        59
      • 1.7.3.5 VRH - Reference Voltage Input Pin

        59
      • 1.7.3.6 Power and Ground Connection Summary

        59
  • 1.8 Device Pinouts

    60
    • 1.8.1 S12GN16 and S12GN32

      60
      • 1.8.1.1 Pinout 20-Pin TSSOP

        60
      • 1.8.1.2 Pinout 32-Pin LQFP

        62
      • 1.8.1.3 Pinout 48-Pin LQFP/QFN

        64
    • 1.8.2 S12GNA16 and S12GNA32

      67
      • 1.8.2.1 Pinout 48-Pin LQFP/QFN

        67
    • 1.8.3 S12GN48

      69
      • 1.8.3.1 Pinout 32-Pin LQFP

        69
      • 1.8.3.2 Pinout 48-Pin LQFP

        72
      • 1.8.3.3 Pinout 64-Pin LQFP

        75
    • 1.8.4 S12G48 and S12G64

      79
      • 1.8.4.1 Pinout 32-Pin LQFP

        79
      • 1.8.4.2 Pinout 48-Pin LQFP

        81
      • 1.8.4.3 Pinout 64-Pin LQFP

        84
    • 1.8.5 S12GA48 and S12GA64

      88
      • 1.8.5.1 Pinout 48-Pin LQFP

        88
      • 1.8.5.2 Pinout 64-Pin LQFP

        91
    • 1.8.6 S12G96 and S12G128

      95
      • 1.8.6.1 Pinout 48-Pin LQFP

        95
      • 1.8.6.2 Pinout 64-Pin LQFP

        98
      • 1.8.6.3 Pinout 100-Pin LQFP

        102
    • 1.8.7 S12GA96 and S12GA128

      107
      • 1.8.7.1 Pinout 48-Pin LQFP

        107
      • 1.8.7.2 Pinout 64-Pin LQFP

        110
      • 1.8.7.3 Pinout 100-Pin LQFP

        114
    • 1.8.8 S12G192 and S12G240

      119
      • 1.8.8.1 Pinout 48-Pin LQFP

        119
      • 1.8.8.2 Pinout 64-Pin LQFP

        122
      • 1.8.8.3 Pinout 100-Pin LQFP

        126
    • 1.8.9 S12GA192 and S12GA240

      131
      • 1.8.9.1 Pinout 48-Pin LQFP

        131
      • 1.8.9.2 Pinout 64-Pin LQFP

        134
      • 1.8.9.3 Pinout 100-Pin LQFP

        138
      • 1.8.9.4 Known Good Die Option (KGD)

        143
  • 1.9 System Clock Description

    146
  • 1.10 Modes of Operation

    146
    • 1.10.1 Chip Configuration Summary

      146
      • 1.10.1.1 Normal Single-Chip Mode

        147
      • 1.10.1.2 Special Single-Chip Mode

        147
    • 1.10.2 Low Power Operation

      147
  • 1.11 Security

    147
  • 1.12 Resets and Interrupts

    147
    • 1.12.1 Resets

      147
    • 1.12.2 Interrupt Vectors

      148
    • 1.12.3 Effects of Reset

      150
      • 1.12.3.1 Flash Configuration Reset Sequence Phase

        150
      • 1.12.3.2 Reset While Flash Command Active

        150
      • 1.12.3.3 I/O Pins

        150
      • 1.12.3.4 RAM

        150
  • 1.13 COP Configuration

    150
  • 1.14 Autonomous Clock (ACLK) Configuration

    151
  • 1.15 ADC External Trigger Input Connection

    151
  • 1.16 ADC Special Conversion Channels

    151
  • 1.17 ADC Result Reference

    152
  • 1.18 ADC VRH/VRL Signal Connection

    152
  • 1.19 BDM Clock Source Connectivity

    153
• Chapter 2 Port Integration Module (S12GPIMV1)

  155
  • 2.1 Introduction

    155
    • 2.1.1 Glossary

      155
    • 2.1.2 Overview

      156
    • 2.1.3 Features

      156
    • 2.1.4 Block Diagram

      157
  • 2.2 PIM Routing - External Signal Description

    157
    • 2.2.1 Package Code

      158
    • 2.2.2 Prioritization

      158
    • 2.2.3 Signals and Priorities

      158
  • 2.3 PIM Routing - Functional description

    160
    • 2.3.1 Pin BKGD

      169
    • 2.3.2 Pins PA7-0

      169
    • 2.3.3 Pins PB7-0

      169
    • 2.3.4 Pins PC7-0

      169
    • 2.3.5 Pins PD7-0

      171
    • 2.3.6 Pins PE1-0

      171
    • 2.3.7 Pins PT7-0

      171
    • 2.3.8 Pins PS7-0

      173
    • 2.3.9 Pins PM3-0

      175
    • 2.3.10 Pins PP7-0

      175
    • 2.3.11 Pins PJ7-0

      177
    • 2.3.12 Pins AD15-0

      178
  • 2.4 PIM Ports - Memory Map and Register Definition

    184
    • 2.4.1 Memory Map

      184
    • 2.4.2 Register Map

      187
      • 2.4.2.1 Block Register Map (G1)

        187
      • 2.4.2.2 Block Register Map (G2)

        192
      • 2.4.2.3 Block Register Map (G3)

        197
    • 2.4.3 Register Descriptions

      202
      • 2.4.3.1 Port A Data Register (PORTA)

        203
      • 2.4.3.2 Port B Data Register (PORTB)

        203
      • 2.4.3.3 Port A Data Direction Register (DDRA)

        204
      • 2.4.3.4 Port B Data Direction Register (DDRB)

        205
      • 2.4.3.5 Port C Data Register (PORTC)

        205
      • 2.4.3.6 Port D Data Register (PORTD)

        206
      • 2.4.3.7 Port C Data Direction Register (DDRC)

        207
      • 2.4.3.8 Port D Data Direction Register (DDRD)

        207
      • 2.4.3.9 Port E Data Register (PORTE)

        208
      • 2.4.3.10 Port E Data Direction Register (DDRE)

        208
      • 2.4.3.11 Ports A, B, C, D, E, BKGD pin Pull Control Register (PUCR)

        209
      • 2.4.3.12 ECLK Control Register (ECLKCTL)

        211
      • 2.4.3.13 IRQ Control Register (IRQCR)

        211
      • 2.4.3.14 Reserved Register

        212
      • 2.4.3.15 Port T Data Register (PTT)

        213
      • 2.4.3.16 Port T Input Register (PTIT)

        213
      • 2.4.3.17 Port T Data Direction Register (DDRT)

        214
      • 2.4.3.18 Port T Pull Device Enable Register (PERT)

        215
      • 2.4.3.19 Port T Polarity Select Register (PPST)

        216
      • 2.4.3.20 Port S Data Register (PTS)

        216
      • 2.4.3.21 Port S Input Register (PTIS)

        217
      • 2.4.3.22 Port S Data Direction Register (DDRS)

        217
      • 2.4.3.23 Port S Pull Device Enable Register (PERS)

        218
      • 2.4.3.24 Port S Polarity Select Register (PPSS)

        218
      • 2.4.3.25 Port S Wired-Or Mode Register (WOMS)

        219
      • 2.4.3.26 Pin Routing Register 0 (PRR0)

        219
      • 2.4.3.27 Port M Data Register (PTM)

        221
      • 2.4.3.28 Port M Input Register (PTIM)

        222
      • 2.4.3.29 Port M Data Direction Register (DDRM)

        222
      • 2.4.3.30 Port M Pull Device Enable Register (PERM)

        223
      • 2.4.3.31 Port M Polarity Select Register (PPSM)

        224
      • 2.4.3.32 Port M Wired-Or Mode Register (WOMM)

        224
      • 2.4.3.33 Package Code Register (PKGCR)

        225
      • 2.4.3.34 Port P Data Register (PTP)

        226
      • 2.4.3.35 Port P Input Register (PTIP)

        227
      • 2.4.3.36 Port P Data Direction Register (DDRP)

        228
      • 2.4.3.37 Port P Pull Device Enable Register (PERP)

        228
      • 2.4.3.38 Port P Polarity Select Register (PPSP)

        229
      • 2.4.3.39 Port P Interrupt Enable Register (PIEP)

        230
      • 2.4.3.40 Port P Interrupt Flag Register (PIFP)

        230
      • 2.4.3.41 Reserved Registers

        232
      • 2.4.3.42 Port J Data Register (PTJ)

        232
      • 2.4.3.43 Port J Input Register (PTIJ)

        233
      • 2.4.3.44 Port J Data Direction Register (DDRJ)

        233
      • 2.4.3.45 Port J Pull Device Enable Register (PERJ)

        234
      • 2.4.3.46 Port J Polarity Select Register (PPSJ)

        235
      • 2.4.3.47 Port J Interrupt Enable Register (PIEJ)

        235
      • 2.4.3.48 Port J Interrupt Flag Register (PIFJ)

        236
      • 2.4.3.49 Port AD Data Register (PT0AD)

        237
      • 2.4.3.50 Port AD Data Register (PT1AD)

        237
      • 2.4.3.51 Port AD Input Register (PTI0AD)

        238
      • 2.4.3.52 Port AD Input Register (PTI1AD)

        238
      • 2.4.3.53 Port AD Data Direction Register (DDR0AD)

        239
      • 2.4.3.54 Port AD Data Direction Register (DDR1AD)

        239
      • 2.4.3.55 Reserved Register

        240
      • 2.4.3.56 Pin Routing Register 1 (PRR1)

        240
      • 2.4.3.57 Port AD Pull Enable Register (PER0AD)

        241
      • 2.4.3.58 Port AD Pull Enable Register (PER1AD)

        242
      • 2.4.3.59 Port AD Polarity Select Register (PPS0AD)

        242
      • 2.4.3.60 Port AD Polarity Select Register (PPS1AD)

        243
      • 2.4.3.61 Port AD Interrupt Enable Register (PIE0AD)

        244
      • 2.4.3.62 Port AD Interrupt Enable Register (PIE1AD)

        244
      • 2.4.3.63 Port AD Interrupt Flag Register (PIF0AD)

        245
      • 2.4.3.64 Port AD Interrupt Flag Register (PIF1AD)

        246
  • 2.5 PIM Ports - Functional Description

    247
    • 2.5.1 General

      247
    • 2.5.2 Registers

      247
      • 2.5.2.1 Data Register (PORTx, PTx)

        247
      • 2.5.2.2 Input Register (PTIx)

        247
      • 2.5.2.3 Data Direction Register (DDRx)

        248
      • 2.5.2.4 Pull Device Enable Register (PERx)

        248
      • 2.5.2.5 Pin Polarity Select Register (PPSx)

        248
      • 2.5.2.6 Wired-Or Mode Register (WOMx)

        249
      • 2.5.2.7 Interrupt Enable Register (PIEx)

        249
      • 2.5.2.8 Interrupt Flag Register (PIFx)

        249
      • 2.5.2.9 Pin Routing Register (PRRx)

        249
      • 2.5.2.10 Package Code Register (PKGCR)

        249
    • 2.5.3 Pin Configuration Summary

      249
    • 2.5.4 Interrupts

      250
      • 2.5.4.1 XIRQ, IRQ Interrupts

        250
      • 2.5.4.2 Pin Interrupts and Wakeup

        251
  • 2.6 Initialization/Application Information

    252
    • 2.6.1 Initialization

      252
    • 2.6.2 Port Data and Data Direction Register writes

      252
    • 2.6.3 Enabling IRQ edge-sensitive mode

      252
    • 2.6.4 ADC External Triggers ETRIG3-0

      252
    • 2.6.5 Emulation of Smaller Packages

      253
• Chapter 3 5V Analog Comparator (ACMPV1)

  255
  • 3.1 Introduction

    255
  • 3.2 Features

    255
  • 3.3 Block Diagram

    255
  • 3.4 External Signals

    256
  • 3.5 Modes of Operation

    256
  • 3.6 Memory Map and Register Definition

    257
    • 3.6.1 Register Map

      257
    • 3.6.2 Register Descriptions

      257
      • 3.6.2.1 ACMP Control Register (ACMPC)

        257
      • 3.6.2.2 ACMP Status Register (ACMPS)

        258
  • 3.7 Functional Description

    259
• Chapter 4 Reference Voltage Attenuator (RVAV1)

  261
  • 4.1 Introduction

    261
  • 4.2 Features

    261
  • 4.3 Block Diagram

    261
  • 4.4 External Signals

    262
  • 4.5 Modes of Operation

    262
  • 4.6 Memory Map and Register Definition

    263
    • 4.6.1 Register Map

      263
    • 4.6.2 Register Descriptions

      263
      • 4.6.2.1 RVA Control Register (RVACTL)

        263
  • 4.7 Functional Description

    264
• Chapter 5 S12G Memory Map Controller (S12GMMCV1)

  265
  • 5.1 Introduction

    265
    • 5.1.1 Glossary

      265
    • 5.1.2 Overview

      265
    • 5.1.3 Features

      266
    • 5.1.4 Modes of Operation

      266
      • 5.1.4.1 Functional Modes

        266
      • 5.1.4.2 Security

        266
    • 5.1.5 Block Diagram

      266
  • 5.2 External Signal Description

    267
  • 5.3 Memory Map and Registers

    267
    • 5.3.1 Module Memory Map

      267
    • 5.3.2 Register Descriptions

      268
      • 5.3.2.1 Mode Register (MODE)

        268
      • 5.3.2.2 Direct Page Register (DIRECT)

        269
      • 5.3.2.3 MMC Control Register (MMCCTL1)

        270
      • 5.3.2.4 Program Page Index Register (PPAGE)

        271
  • 5.4 Functional Description

    272
    • 5.4.1 MCU Operating Modes

      272
    • 5.4.2 Memory Map Scheme

      272
      • 5.4.2.1 CPU and BDM Memory Map Scheme

        272
    • 5.4.3 Unimplemented and Reserved Address Ranges

      276
    • 5.4.4 Prioritization of Memory Accesses

      277
    • 5.4.5 Interrupts

      277
• Chapter 6 Interrupt Module (S12SINTV1)

  279
  • 6.1 Introduction

    279
    • 6.1.1 Glossary

      279
    • 6.1.2 Features

      279
    • 6.1.3 Modes of Operation

      280
    • 6.1.4 Block Diagram

      280
  • 6.2 External Signal Description

    281
  • 6.3 Memory Map and Register Definition

    281
    • 6.3.1 Register Descriptions

      281
      • 6.3.1.1 Interrupt Vector Base Register (IVBR)

        281
  • 6.4 Functional Description

    282
    • 6.4.1 S12S Exception Requests

      282
    • 6.4.2 Interrupt Prioritization

      282
    • 6.4.3 Reset Exception Requests

      283
    • 6.4.4 Exception Priority

      283
  • 6.5 Initialization/Application Information

    284
    • 6.5.1 Initialization

      284
    • 6.5.2 Interrupt Nesting

      284
    • 6.5.3 Wake Up from Stop or Wait Mode

      284
      • 6.5.3.1 CPU Wake Up from Stop or Wait Mode

        284
• Chapter 7 Background Debug Module (S12SBDMV1)

  287
  • 7.1 Introduction

    287
    • 7.1.1 Features

      287
    • 7.1.2 Modes of Operation

      288
      • 7.1.2.1 Regular Run Modes

        288
      • 7.1.2.2 Secure Mode Operation

        288
      • 7.1.2.3 Low-Power Modes

        288
    • 7.1.3 Block Diagram

      289
  • 7.2 External Signal Description

    289
  • 7.3 Memory Map and Register Definition

    289
    • 7.3.1 Module Memory Map

      289
    • 7.3.2 Register Descriptions

      290
      • 7.3.2.1 BDM Status Register (BDMSTS)

        291
      • 7.3.2.2 BDM Program Page Index Register (BDMPPR)

        293
    • 7.3.3 Family ID Assignment

      294
  • 7.4 Functional Description

    294
    • 7.4.1 Security

      294
    • 7.4.2 Enabling and Activating BDM

      294
    • 7.4.3 BDM Hardware Commands

      295
    • 7.4.4 Standard BDM Firmware Commands

      296
    • 7.4.5 BDM Command Structure

      297
    • 7.4.6 BDM Serial Interface

      299
    • 7.4.7 Serial Interface Hardware Handshake Protocol

      302
    • 7.4.8 Hardware Handshake Abort Procedure

      304
    • 7.4.9 SYNC - Request Timed Reference Pulse

      307
    • 7.4.10 Instruction Tracing

      307
    • 7.4.11 Serial Communication Time Out

      308
• Chapter 8 S12S Debug Module (S12SDBGV2)

  311
  • 8.1 Introduction

    311
    • 8.1.1 Glossary Of Terms

      311
    • 8.1.2 Overview

      312
    • 8.1.3 Features

      312
    • 8.1.4 Modes of Operation

      313
    • 8.1.5 Block Diagram

      313
  • 8.2 External Signal Description

    314
  • 8.3 Memory Map and Registers

    314
    • 8.3.1 Module Memory Map

      314
    • 8.3.2 Register Descriptions

      315
      • 8.3.2.1 Debug Control Register 1 (DBGC1)

        315
      • 8.3.2.2 Debug Status Register (DBGSR)

        316
      • 8.3.2.3 Debug Trace Control Register (DBGTCR)

        317
      • 8.3.2.4 Debug Control Register2 (DBGC2)

        318
      • 8.3.2.5 Debug Trace Buffer Register (DBGTBH:DBGTBL)

        319
      • 8.3.2.6 Debug Count Register (DBGCNT)

        319
      • 8.3.2.7 Debug State Control Registers

        320
      • 8.3.2.8 Comparator Register Descriptions

        324
  • 8.4 Functional Description

    330
    • 8.4.1 S12SDBG Operation

      331
    • 8.4.2 Comparator Modes

      331
      • 8.4.2.1 Single Address Comparator Match

        332
      • 8.4.2.2 Range Comparisons

        334
    • 8.4.3 Match Modes (Forced or Tagged)

      335
      • 8.4.3.1 Forced Match

        335
      • 8.4.3.2 Tagged Match

        335
      • 8.4.3.3 Immediate Trigger

        336
      • 8.4.3.4 Channel Priorities

        336
    • 8.4.4 State Sequence Control

      336
      • 8.4.4.1 Final State

        337
    • 8.4.5 Trace Buffer Operation

      337
      • 8.4.5.1 Trace Trigger Alignment

        337
      • 8.4.5.2 Trace Modes

        338
      • 8.4.5.3 Trace Buffer Organization (Normal, Loop1, Detail modes)

        340
      • 8.4.5.4 Trace Buffer Organization (Compressed Pure PC mode)

        342
      • 8.4.5.5 Reading Data from Trace Buffer

        343
      • 8.4.5.6 Trace Buffer Reset State

        343
    • 8.4.6 Tagging

      344
    • 8.4.7 Breakpoints

      344
      • 8.4.7.1 Breakpoints From Comparator Channels

        344
      • 8.4.7.2 Breakpoints Generated Via The TRIG Bit

        345
      • 8.4.7.3 Breakpoint Priorities

        345
  • 8.5 Application Information

    346
    • 8.5.1 State Machine scenarios

      346
    • 8.5.2 Scenario 1

      346
    • 8.5.3 Scenario 2

      347
    • 8.5.4 Scenario 3

      347
    • 8.5.5 Scenario 4

      347
    • 8.5.6 Scenario 5

      349
    • 8.5.7 Scenario 6

      349
    • 8.5.8 Scenario 7

      349
    • 8.5.9 Scenario 8

      350
    • 8.5.10 Scenario 9

      350
    • 8.5.11 Scenario 10

      350
• Chapter 9 Security (S12XS9SECV2)

  353
  • 9.1 Introduction

    353
    • 9.1.1 Features

      353
    • 9.1.2 Modes of Operation

      353
    • 9.1.3 Securing the Microcontroller

      354
    • 9.1.4 Operation of the Secured Microcontroller

      355
      • 9.1.4.1 Normal Single Chip Mode (NS)

        355
      • 9.1.4.2 Special Single Chip Mode (SS)

        355
    • 9.1.5 Unsecuring the Microcontroller

      356
      • 9.1.5.1 Unsecuring the MCU Using the Backdoor Key Access

        356
    • 9.1.6 Reprogramming the Security Bits

      356
    • 9.1.7 Complete Memory Erase (Special Modes)

      357
• Chapter 10 S12 Clock, Reset and Power Management Unit (S12CPMU)

  359
  • 10.1 Introduction

    359
    • 10.1.1 Features

      359
    • 10.1.2 Modes of Operation

      362
      • 10.1.2.1 Run Mode

        362
      • 10.1.2.2 Wait Mode

        362
      • 10.1.2.3 Stop Mode

        364
    • 10.1.3 S12CPMU Block Diagram

      365
  • 10.2 Signal Description

    367
    • 10.2.1 RESET

      367
    • 10.2.2 EXTAL and XTAL

      367
    • 10.2.3 VDDR - Regulator Power Input Pin

      367
    • 10.2.4 VSS - Ground Pin

      367
    • 10.2.5 VDDA, VSSA - Regulator Reference Supply Pins

      367
    • 10.2.6 VDDX, VSSX- Pad Supply Pins

      367
    • 10.2.7 VDD - Internal Regulator Output Supply (Core Logic)

      368
    • 10.2.8 VDDF - Internal Regulator Output Supply (NVM Logic)

      368
    • 10.2.9 API_EXTCLK - API external clock output pin

      368
  • 10.3 Memory Map and Registers

    369
    • 10.3.1 Module Memory Map

      369
    • 10.3.2 Register Descriptions

      371
      • 10.3.2.1 S12CPMU Synthesizer Register (CPMUSYNR)

        371
      • 10.3.2.2 S12CPMU Reference Divider Register (CPMUREFDIV)

        372
      • 10.3.2.3 S12CPMU Post Divider Register (CPMUPOSTDIV)

        373
      • 10.3.2.4 S12CPMU Flags Register (CPMUFLG)

        373
      • 10.3.2.5 S12CPMU Interrupt Enable Register (CPMUINT)

        375
      • 10.3.2.6 S12CPMU Clock Select Register (CPMUCLKS)

        376
      • 10.3.2.7 S12CPMU PLL Control Register (CPMUPLL)

        379
      • 10.3.2.8 S12CPMU RTI Control Register (CPMURTI)

        380
      • 10.3.2.9 S12CPMU COP Control Register (CPMUCOP)

        383
      • 10.3.2.10 Reserved Register CPMUTEST0

        386
      • 10.3.2.11 Reserved Register CPMUTEST1

        386
      • 10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)

        387
      • 10.3.2.13 Low Voltage Control Register (CPMULVCTL)

        388
      • 10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)

        389
      • 10.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR)

        391
      • 10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register (CPMUAPIRH / CPMUAPIRL)

        392
      • 10.3.2.17 Reserved Register CPMUTEST3

        394
      • 10.3.2.18 S12CPMU IRC1M Trim Registers (CPMUIRCTRIMH / CPMUIRCTRIML)

        395
      • 10.3.2.19 S12CPMU Oscillator Register (CPMUOSC)

        399
      • 10.3.2.20 S12CPMU Protection Register (CPMUPROT)

        401
      • 10.3.2.21 Reserved Register CPMUTEST2

        402
  • 10.4 Functional Description

    403
    • 10.4.1 Phase Locked Loop with Internal Filter (PLL)

      403
    • 10.4.2 Startup from Reset

      405
    • 10.4.3 Stop Mode using PLLCLK as Bus Clock

      405
    • 10.4.4 Full Stop Mode using Oscillator Clock as Bus Clock

      406
    • 10.4.5 External Oscillator

      407
      • 10.4.5.1 Enabling the External Oscillator

        407
    • 10.4.6 System Clock Configurations

      408
      • 10.4.6.1 PLL Engaged Internal Mode (PEI)

        408
      • 10.4.6.2 PLL Engaged External Mode (PEE)

        408
      • 10.4.6.3 PLL Bypassed External Mode (PBE)

        408
  • 10.5 Resets

    409
    • 10.5.1 General

      409
    • 10.5.2 Description of Reset Operation

      409
      • 10.5.2.1 Clock Monitor Reset

        410
      • 10.5.2.2 Computer Operating Properly Watchdog (COP) Reset

        411
    • 10.5.3 Power-On Reset (POR)

      412
    • 10.5.4 Low-Voltage Reset (LVR)

      412
  • 10.6 Interrupts

    412
    • 10.6.1 Description of Interrupt Operation

      412
      • 10.6.1.1 Real Time Interrupt (RTI)

        412
      • 10.6.1.2 PLL Lock Interrupt

        413
      • 10.6.1.3 Oscillator Status Interrupt

        413
      • 10.6.1.4 Low-Voltage Interrupt (LVI)

        413
      • 10.6.1.5 Autonomous Periodical Interrupt (API)

        413
  • 10.7 Initialization/Application Information

    414
    • 10.7.1 General Initialization information

      414
    • 10.7.2 Application information for COP and API usage

      414
• Chapter 11 Analog-to-Digital Converter (ADC10B8CV2)

  417
  • 11.1 Introduction

    417
    • 11.1.1 Features

      418
    • 11.1.2 Modes of Operation

      419
      • 11.1.2.1 Conversion Modes

        419
      • 11.1.2.2 MCU Operating Modes

        419
    • 11.1.3 Block Diagram

      420
  • 11.2 Signal Description

    421
    • 11.2.1 Detailed Signal Descriptions

      421
      • 11.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)

        421
      • 11.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        421
      • 11.2.1.3 VRH, VRL

        421
      • 11.2.1.4 VDDA, VSSA

        421
  • 11.3 Memory Map and Register Definition

    421
    • 11.3.1 Module Memory Map

      421
    • 11.3.2 Register Descriptions

      423
      • 11.3.2.1 ATD Control Register 0 (ATDCTL0)

        423
      • 11.3.2.2 ATD Control Register 1 (ATDCTL1)

        424
      • 11.3.2.3 ATD Control Register 2 (ATDCTL2)

        425
      • 11.3.2.4 ATD Control Register 3 (ATDCTL3)

        427
      • 11.3.2.5 ATD Control Register 4 (ATDCTL4)

        429
      • 11.3.2.6 ATD Control Register 5 (ATDCTL5)

        430
      • 11.3.2.7 ATD Status Register 0 (ATDSTAT0)

        432
      • 11.3.2.8 ATD Compare Enable Register (ATDCMPE)

        433
      • 11.3.2.9 ATD Status Register 2 (ATDSTAT2)

        434
      • 11.3.2.10 ATD Input Enable Register (ATDDIEN)

        435
      • 11.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        435
      • 11.3.2.12 ATD Conversion Result Registers (ATDDRn)

        436
  • 11.4 Functional Description

    438
    • 11.4.1 Analog Sub-Block

      438
      • 11.4.1.1 Sample and Hold Machine

        438
      • 11.4.1.2 Analog Input Multiplexer

        438
      • 11.4.1.3 Analog-to-Digital (A/D) Machine

        438
    • 11.4.2 Digital Sub-Block

      438
      • 11.4.2.1 External Trigger Input

        438
      • 11.4.2.2 General-Purpose Digital Port Operation

        439
  • 11.5 Resets

    440
  • 11.6 Interrupts

    440
• Chapter 12 Analog-to-Digital Converter (ADC12B8CV2)

  441
  • 12.1 Introduction

    441
    • 12.1.1 Features

      442
    • 12.1.2 Modes of Operation

      443
      • 12.1.2.1 Conversion Modes

        443
      • 12.1.2.2 MCU Operating Modes

        443
    • 12.1.3 Block Diagram

      444
  • 12.2 Signal Description

    445
    • 12.2.1 Detailed Signal Descriptions

      445
      • 12.2.1.1 ANx (x = 7, 6, 5, 4, 3, 2, 1, 0)

        445
      • 12.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        445
      • 12.2.1.3 VRH, VRL

        445
      • 12.2.1.4 VDDA, VSSA

        445
  • 12.3 Memory Map and Register Definition

    445
    • 12.3.1 Module Memory Map

      445
    • 12.3.2 Register Descriptions

      447
      • 12.3.2.1 ATD Control Register 0 (ATDCTL0)

        447
      • 12.3.2.2 ATD Control Register 1 (ATDCTL1)

        448
      • 12.3.2.3 ATD Control Register 2 (ATDCTL2)

        449
      • 12.3.2.4 ATD Control Register 3 (ATDCTL3)

        451
      • 12.3.2.5 ATD Control Register 4 (ATDCTL4)

        453
      • 12.3.2.6 ATD Control Register 5 (ATDCTL5)

        454
      • 12.3.2.7 ATD Status Register 0 (ATDSTAT0)

        457
      • 12.3.2.8 ATD Compare Enable Register (ATDCMPE)

        458
      • 12.3.2.9 ATD Status Register 2 (ATDSTAT2)

        459
      • 12.3.2.10 ATD Input Enable Register (ATDDIEN)

        460
      • 12.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        460
      • 12.3.2.12 ATD Conversion Result Registers (ATDDRn)

        461
  • 12.4 Functional Description

    463
    • 12.4.1 Analog Sub-Block

      463
      • 12.4.1.1 Sample and Hold Machine

        463
      • 12.4.1.2 Analog Input Multiplexer

        463
      • 12.4.1.3 Analog-to-Digital (A/D) Machine

        463
    • 12.4.2 Digital Sub-Block

      463
      • 12.4.2.1 External Trigger Input

        463
      • 12.4.2.2 General-Purpose Digital Port Operation

        464
  • 12.5 Resets

    465
  • 12.6 Interrupts

    465
• Chapter 13 Analog-to-Digital Converter (ADC10B12CV2)

  467
  • 13.1 Introduction

    468
    • 13.1.1 Features

      468
    • 13.1.2 Modes of Operation

      469
      • 13.1.2.1 Conversion Modes

        469
      • 13.1.2.2 MCU Operating Modes

        469
    • 13.1.3 Block Diagram

      470
  • 13.2 Signal Description

    471
    • 13.2.1 Detailed Signal Descriptions

      471
      • 13.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)

        471
      • 13.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        471
      • 13.2.1.3 VRH, VRL

        471
      • 13.2.1.4 VDDA, VSSA

        471
  • 13.3 Memory Map and Register Definition

    471
    • 13.3.1 Module Memory Map

      471
    • 13.3.2 Register Descriptions

      474
      • 13.3.2.1 ATD Control Register 0 (ATDCTL0)

        474
      • 13.3.2.2 ATD Control Register 1 (ATDCTL1)

        475
      • 13.3.2.3 ATD Control Register 2 (ATDCTL2)

        476
      • 13.3.2.4 ATD Control Register 3 (ATDCTL3)

        478
      • 13.3.2.5 ATD Control Register 4 (ATDCTL4)

        480
      • 13.3.2.6 ATD Control Register 5 (ATDCTL5)

        481
      • 13.3.2.7 ATD Status Register 0 (ATDSTAT0)

        483
      • 13.3.2.8 ATD Compare Enable Register (ATDCMPE)

        484
      • 13.3.2.9 ATD Status Register 2 (ATDSTAT2)

        485
      • 13.3.2.10 ATD Input Enable Register (ATDDIEN)

        486
      • 13.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        486
      • 13.3.2.12 ATD Conversion Result Registers (ATDDRn)

        487
  • 13.4 Functional Description

    489
    • 13.4.1 Analog Sub-Block

      489
      • 13.4.1.1 Sample and Hold Machine

        489
      • 13.4.1.2 Analog Input Multiplexer

        489
      • 13.4.1.3 Analog-to-Digital (A/D) Machine

        489
    • 13.4.2 Digital Sub-Block

      489
      • 13.4.2.1 External Trigger Input

        489
      • 13.4.2.2 General-Purpose Digital Port Operation

        490
  • 13.5 Resets

    491
  • 13.6 Interrupts

    491
• Chapter 14 Analog-to-Digital Converter (ADC12B12CV2)

  493
  • 14.1 Introduction

    494
    • 14.1.1 Features

      494
    • 14.1.2 Modes of Operation

      495
      • 14.1.2.1 Conversion Modes

        495
      • 14.1.2.2 MCU Operating Modes

        495
    • 14.1.3 Block Diagram

      496
  • 14.2 Signal Description

    497
    • 14.2.1 Detailed Signal Descriptions

      497
      • 14.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)

        497
      • 14.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        497
      • 14.2.1.3 VRH, VRL

        497
      • 14.2.1.4 VDDA, VSSA

        497
  • 14.3 Memory Map and Register Definition

    497
    • 14.3.1 Module Memory Map

      497
    • 14.3.2 Register Descriptions

      500
      • 14.3.2.1 ATD Control Register 0 (ATDCTL0)

        500
      • 14.3.2.2 ATD Control Register 1 (ATDCTL1)

        501
      • 14.3.2.3 ATD Control Register 2 (ATDCTL2)

        502
      • 14.3.2.4 ATD Control Register 3 (ATDCTL3)

        504
      • 14.3.2.5 ATD Control Register 4 (ATDCTL4)

        506
      • 14.3.2.6 ATD Control Register 5 (ATDCTL5)

        507
      • 14.3.2.7 ATD Status Register 0 (ATDSTAT0)

        510
      • 14.3.2.8 ATD Compare Enable Register (ATDCMPE)

        511
      • 14.3.2.9 ATD Status Register 2 (ATDSTAT2)

        512
      • 14.3.2.10 ATD Input Enable Register (ATDDIEN)

        513
      • 14.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        513
      • 14.3.2.12 ATD Conversion Result Registers (ATDDRn)

        514
  • 14.4 Functional Description

    516
    • 14.4.1 Analog Sub-Block

      516
      • 14.4.1.1 Sample and Hold Machine

        516
      • 14.4.1.2 Analog Input Multiplexer

        516
      • 14.4.1.3 Analog-to-Digital (A/D) Machine

        516
    • 14.4.2 Digital Sub-Block

      516
      • 14.4.2.1 External Trigger Input

        516
      • 14.4.2.2 General-Purpose Digital Port Operation

        517
  • 14.5 Resets

    518
  • 14.6 Interrupts

    518
• Chapter 15 Analog-to-Digital Converter (ADC10B16CV2)

  519
  • 15.1 Introduction

    520
    • 15.1.1 Features

      520
    • 15.1.2 Modes of Operation

      521
      • 15.1.2.1 Conversion Modes

        521
      • 15.1.2.2 MCU Operating Modes

        521
    • 15.1.3 Block Diagram

      522
  • 15.2 Signal Description

    523
    • 15.2.1 Detailed Signal Descriptions

      523
      • 15.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)

        523
      • 15.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        523
      • 15.2.1.3 VRH, VRL

        523
      • 15.2.1.4 VDDA, VSSA

        523
  • 15.3 Memory Map and Register Definition

    523
    • 15.3.1 Module Memory Map

      523
    • 15.3.2 Register Descriptions

      526
      • 15.3.2.1 ATD Control Register 0 (ATDCTL0)

        526
      • 15.3.2.2 ATD Control Register 1 (ATDCTL1)

        527
      • 15.3.2.3 ATD Control Register 2 (ATDCTL2)

        528
      • 15.3.2.4 ATD Control Register 3 (ATDCTL3)

        530
      • 15.3.2.5 ATD Control Register 4 (ATDCTL4)

        532
      • 15.3.2.6 ATD Control Register 5 (ATDCTL5)

        533
      • 15.3.2.7 ATD Status Register 0 (ATDSTAT0)

        535
      • 15.3.2.8 ATD Compare Enable Register (ATDCMPE)

        536
      • 15.3.2.9 ATD Status Register 2 (ATDSTAT2)

        537
      • 15.3.2.10 ATD Input Enable Register (ATDDIEN)

        538
      • 15.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        538
      • 15.3.2.12 ATD Conversion Result Registers (ATDDRn)

        539
  • 15.4 Functional Description

    541
    • 15.4.1 Analog Sub-Block

      541
      • 15.4.1.1 Sample and Hold Machine

        541
      • 15.4.1.2 Analog Input Multiplexer

        541
      • 15.4.1.3 Analog-to-Digital (A/D) Machine

        541
    • 15.4.2 Digital Sub-Block

      541
      • 15.4.2.1 External Trigger Input

        541
      • 15.4.2.2 General-Purpose Digital Port Operation

        542
  • 15.5 Resets

    543
  • 15.6 Interrupts

    543
• Chapter 16 Analog-to-Digital Converter (ADC12B16CV2)

  545
  • 16.1 Introduction

    546
    • 16.1.1 Features

      546
    • 16.1.2 Modes of Operation

      547
      • 16.1.2.1 Conversion Modes

        547
      • 16.1.2.2 MCU Operating Modes

        547
    • 16.1.3 Block Diagram

      548
  • 16.2 Signal Description

    549
    • 16.2.1 Detailed Signal Descriptions

      549
      • 16.2.1.1 ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)

        549
      • 16.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0

        549
      • 16.2.1.3 VRH, VRL

        549
      • 16.2.1.4 VDDA, VSSA

        549
  • 16.3 Memory Map and Register Definition

    549
    • 16.3.1 Module Memory Map

      549
    • 16.3.2 Register Descriptions

      552
      • 16.3.2.1 ATD Control Register 0 (ATDCTL0)

        552
      • 16.3.2.2 ATD Control Register 1 (ATDCTL1)

        553
      • 16.3.2.3 ATD Control Register 2 (ATDCTL2)

        554
      • 16.3.2.4 ATD Control Register 3 (ATDCTL3)

        556
      • 16.3.2.5 ATD Control Register 4 (ATDCTL4)

        558
      • 16.3.2.6 ATD Control Register 5 (ATDCTL5)

        559
      • 16.3.2.7 ATD Status Register 0 (ATDSTAT0)

        562
      • 16.3.2.8 ATD Compare Enable Register (ATDCMPE)

        563
      • 16.3.2.9 ATD Status Register 2 (ATDSTAT2)

        564
      • 16.3.2.10 ATD Input Enable Register (ATDDIEN)

        565
      • 16.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)

        565
      • 16.3.2.12 ATD Conversion Result Registers (ATDDRn)

        566
  • 16.4 Functional Description

    568
    • 16.4.1 Analog Sub-Block

      568
      • 16.4.1.1 Sample and Hold Machine

        568
      • 16.4.1.2 Analog Input Multiplexer

        568
      • 16.4.1.3 Analog-to-Digital (A/D) Machine

        568
    • 16.4.2 Digital Sub-Block

      568
      • 16.4.2.1 External Trigger Input

        568
      • 16.4.2.2 General-Purpose Digital Port Operation

        569
  • 16.5 Resets

    570
  • 16.6 Interrupts

    570
• Chapter 17 Digital Analog Converter (DAC_8B5V)

  571
  • 17.1 Revision History

    571
  • 17.2 Introduction

    572
    • 17.2.1 Features

      572
    • 17.2.2 Modes of Operation

      572
    • 17.2.3 Block Diagram

      573
  • 17.3 External Signal Description

    573
    • 17.3.1 DACU Output Pin

      573
    • 17.3.2 AMP Output Pin

      573
    • 17.3.3 AMPP Input Pin

      573
    • 17.3.4 AMPM Input Pin

      574
  • 17.4 Memory Map and Register Definition

    574
    • 17.4.1 Register Summary

      574
    • 17.4.2 Register Descriptions

      574
      • 17.4.2.1 Control Register (DACCTL)

        575
      • 17.4.2.2 Analog Output Voltage Level Register (DACVOL)

        576
      • 17.4.2.3 Reserved Register

        576
  • 17.5 Functional Description

    576
    • 17.5.1 Functional Overview

      576
    • 17.5.2 Mode “Off”

      577
    • 17.5.3 Mode “Operational Amplifier”

      577
    • 17.5.4 Mode “Unbuffered DAC”

      578
    • 17.5.5 Mode “Unbuffered DAC with Operational Amplifier”

      578
    • 17.5.6 Mode “Buffered DAC”

      578
    • 17.5.7 Analog output voltage calculation

      578
• Chapter 18 Freescale’s Scalable Controller Area Network (S12MSCANV3)

  583
  • 18.1 Introduction

    583
    • 18.1.1 Glossary

      584
    • 18.1.2 Block Diagram

      584
    • 18.1.3 Features

      585
    • 18.1.4 Modes of Operation

      585
  • 18.2 External Signal Description

    585
    • 18.2.1 RXCAN - CAN Receiver Input Pin

      585
    • 18.2.2 TXCAN - CAN Transmitter Output Pin

      586
    • 18.2.3 CAN System

      586
  • 18.3 Memory Map and Register Definition

    586
    • 18.3.1 Module Memory Map

      586
    • 18.3.2 Register Descriptions

      588
      • 18.3.2.1 MSCAN Control Register 0 (CANCTL0)

        588
      • 18.3.2.2 MSCAN Control Register 1 (CANCTL1)

        590
      • 18.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

        592
      • 18.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)

        593
      • 18.3.2.5 MSCAN Receiver Flag Register (CANRFLG)

        594
      • 18.3.2.6 MSCAN Receiver Interrupt Enable Register (CANRIER)

        596
      • 18.3.2.7 MSCAN Transmitter Flag Register (CANTFLG)

        597
      • 18.3.2.8 MSCAN Transmitter Interrupt Enable Register (CANTIER)

        598
      • 18.3.2.9 MSCAN Transmitter Message Abort Request Register (CANTARQ)

        599
      • 18.3.2.10 MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)

        600
      • 18.3.2.11 MSCAN Transmit Buffer Selection Register (CANTBSEL)

        600
      • 18.3.2.12 MSCAN Identifier Acceptance Control Register (CANIDAC)

        601
      • 18.3.2.13 MSCAN Reserved Register

        602
      • 18.3.2.14 MSCAN Miscellaneous Register (CANMISC)

        603
      • 18.3.2.15 MSCAN Receive Error Counter (CANRXERR)

        603
      • 18.3.2.16 MSCAN Transmit Error Counter (CANTXERR)

        604
      • 18.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)

        604
      • 18.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0-CANIDMR7)

        605
    • 18.3.3 Programmer’s Model of Message Storage

      607
      • 18.3.3.1 Identifier Registers (IDR0-IDR3)

        609
      • 18.3.3.2 Data Segment Registers (DSR0-7)

        613
      • 18.3.3.3 Data Length Register (DLR)

        613
      • 18.3.3.4 Transmit Buffer Priority Register (TBPR)

        614
      • 18.3.3.5 Time Stamp Register (TSRH-TSRL)

        615
  • 18.4 Functional Description

    616
    • 18.4.1 General

      616
    • 18.4.2 Message Storage

      617
      • 18.4.2.1 Message Transmit Background

        617
      • 18.4.2.2 Transmit Structures

        618
      • 18.4.2.3 Receive Structures

        619
    • 18.4.3 Identifier Acceptance Filter

      620
      • 18.4.3.1 Protocol Violation Protection

        624
      • 18.4.3.2 Clock System

        624
    • 18.4.4 Modes of Operation

      626
      • 18.4.4.1 Normal System Operating Modes

        626
      • 18.4.4.2 Special System Operating Modes

        627
      • 18.4.4.3 Emulation Modes

        627
      • 18.4.4.4 Listen-Only Mode

        627
      • 18.4.4.5 MSCAN Initialization Mode

        627
    • 18.4.5 Low-Power Options

      628
      • 18.4.5.1 Operation in Run Mode

        629
      • 18.4.5.2 Operation in Wait Mode

        629
      • 18.4.5.3 Operation in Stop Mode

        629
      • 18.4.5.4 MSCAN Normal Mode

        629
      • 18.4.5.5 MSCAN Sleep Mode

        630
      • 18.4.5.6 MSCAN Power Down Mode

        631
      • 18.4.5.7 Disabled Mode

        632
      • 18.4.5.8 Programmable Wake-Up Function

        632
    • 18.4.6 Reset Initialization

      632
    • 18.4.7 Interrupts

      632
      • 18.4.7.1 Description of Interrupt Operation

        632
      • 18.4.7.2 Transmit Interrupt

        632
      • 18.4.7.3 Receive Interrupt

        633
      • 18.4.7.4 Wake-Up Interrupt

        633
      • 18.4.7.5 Error Interrupt

        633
      • 18.4.7.6 Interrupt Acknowledge

        633
  • 18.5 Initialization/Application Information

    634
    • 18.5.1 MSCAN initialization

      634
    • 18.5.2 Bus-Off Recovery

      634
• Chapter 19 Pulse-Width Modulator (S12PWM8B8CV2)

  635
  • 19.1 Introduction

    635
    • 19.1.1 Features

      635
    • 19.1.2 Modes of Operation

      635
    • 19.1.3 Block Diagram

      636
  • 19.2 External Signal Description

    636
    • 19.2.1 PWM7 - PWM0 - PWM Channel 7 - 0

      636
  • 19.3 Memory Map and Register Definition

    637
    • 19.3.1 Module Memory Map

      637
    • 19.3.2 Register Descriptions

      637
      • 19.3.2.1 PWM Enable Register (PWME)

        640
      • 19.3.2.2 PWM Polarity Register (PWMPOL)

        641
      • 19.3.2.3 PWM Clock Select Register (PWMCLK)

        642
      • 19.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)

        643
      • 19.3.2.5 PWM Center Align Enable Register (PWMCAE)

        644
      • 19.3.2.6 PWM Control Register (PWMCTL)

        645
      • 19.3.2.7 PWM Clock A/B Select Register (PWMCLKAB)

        646
      • 19.3.2.8 PWM Scale A Register (PWMSCLA)

        648
      • 19.3.2.9 PWM Scale B Register (PWMSCLB)

        648
      • 19.3.2.10 PWM Channel Counter Registers (PWMCNTx)

        649
      • 19.3.2.11 PWM Channel Period Registers (PWMPERx)

        649
      • 19.3.2.12 PWM Channel Duty Registers (PWMDTYx)

        650
  • 19.4 Functional Description

    652
    • 19.4.1 PWM Clock Select

      652
      • 19.4.1.1 Prescale

        652
      • 19.4.1.2 Clock Scale

        652
      • 19.4.1.3 Clock Select

        654
    • 19.4.2 PWM Channel Timers

      655
      • 19.4.2.1 PWM Enable

        655
      • 19.4.2.2 PWM Polarity

        656
      • 19.4.2.3 PWM Period and Duty

        656
      • 19.4.2.4 PWM Timer Counters

        656
      • 19.4.2.5 Left Aligned Outputs

        657
      • 19.4.2.6 Center Aligned Outputs

        659
      • 19.4.2.7 PWM 16-Bit Functions

        660
      • 19.4.2.8 PWM Boundary Cases

        662
  • 19.5 Resets

    662
  • 19.6 Interrupts

    663
• Chapter 20 Serial Communication Interface (S12SCIV5)

  665
  • 20.1 Introduction

    665
    • 20.1.1 Glossary

      665
    • 20.1.2 Features

      666
    • 20.1.3 Modes of Operation

      666
    • 20.1.4 Block Diagram

      667
  • 20.2 External Signal Description

    667
    • 20.2.1 TXD - Transmit Pin

      667
    • 20.2.2 RXD - Receive Pin

      667
  • 20.3 Memory Map and Register Definition

    667
    • 20.3.1 Module Memory Map and Register Definition

      668
    • 20.3.2 Register Descriptions

      668
      • 20.3.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL)

        669
      • 20.3.2.2 SCI Control Register 1 (SCICR1)

        670
      • 20.3.2.3 SCI Alternative Status Register 1 (SCIASR1)

        672
      • 20.3.2.4 SCI Alternative Control Register 1 (SCIACR1)

        672
      • 20.3.2.5 SCI Alternative Control Register 2 (SCIACR2)

        673
      • 20.3.2.6 SCI Control Register 2 (SCICR2)

        674
      • 20.3.2.7 SCI Status Register 1 (SCISR1)

        675
      • 20.3.2.8 SCI Status Register 2 (SCISR2)

        677
      • 20.3.2.9 SCI Data Registers (SCIDRH, SCIDRL)

        678
  • 20.4 Functional Description

    679
    • 20.4.1 Infrared Interface Submodule

      680
      • 20.4.1.1 Infrared Transmit Encoder

        681
      • 20.4.1.2 Infrared Receive Decoder

        681
    • 20.4.2 LIN Support

      681
    • 20.4.3 Data Format

      681
    • 20.4.4 Baud Rate Generation

      683
    • 20.4.5 Transmitter

      684
      • 20.4.5.1 Transmitter Character Length

        684
      • 20.4.5.2 Character Transmission

        684
      • 20.4.5.3 Break Characters

        686
      • 20.4.5.4 Idle Characters

        687
      • 20.4.5.5 LIN Transmit Collision Detection

        688
    • 20.4.6 Receiver

      689
      • 20.4.6.1 Receiver Character Length

        689
      • 20.4.6.2 Character Reception

        689
      • 20.4.6.3 Data Sampling

        690
      • 20.4.6.4 Framing Errors

        694
      • 20.4.6.5 Baud Rate Tolerance

        694
      • 20.4.6.6 Receiver Wakeup

        696
    • 20.4.7 Single-Wire Operation

      697
    • 20.4.8 Loop Operation

      698
  • 20.5 Initialization/Application Information

    698
    • 20.5.1 Reset Initialization

      698
    • 20.5.2 Modes of Operation

      698
      • 20.5.2.1 Run Mode

        698
      • 20.5.2.2 Wait Mode

        698
      • 20.5.2.3 Stop Mode

        699
    • 20.5.3 Interrupt Operation

      699
      • 20.5.3.1 Description of Interrupt Operation

        699
    • 20.5.4 Recovery from Wait Mode

      701
    • 20.5.5 Recovery from Stop Mode

      701
• Chapter 21 Serial Peripheral Interface (S12SPIV5)

  703
  • 21.1 Introduction

    703
    • 21.1.1 Glossary of Terms

      703
    • 21.1.2 Features

      703
    • 21.1.3 Modes of Operation

      704
    • 21.1.4 Block Diagram

      704
  • 21.2 External Signal Description

    705
    • 21.2.1 MOSI - Master Out/Slave In Pin

      705
    • 21.2.2 MISO - Master In/Slave Out Pin

      706
    • 21.2.3 SS - Slave Select Pin

      706
    • 21.2.4 SCK - Serial Clock Pin

      706
  • 21.3 Memory Map and Register Definition

    706
    • 21.3.1 Module Memory Map

      706
    • 21.3.2 Register Descriptions

      707
      • 21.3.2.1 SPI Control Register 1 (SPICR1)

        707
      • 21.3.2.2 SPI Control Register 2 (SPICR2)

        708
      • 21.3.2.3 SPI Baud Rate Register (SPIBR)

        710
      • 21.3.2.4 SPI Status Register (SPISR)

        712
      • 21.3.2.5 SPI Data Register (SPIDR = SPIDRH:SPIDRL)

        714
  • 21.4 Functional Description

    715
    • 21.4.1 Master Mode

      716
    • 21.4.2 Slave Mode

      717
    • 21.4.3 Transmission Formats

      718
      • 21.4.3.1 Clock Phase and Polarity Controls

        719
      • 21.4.3.2 CPHA = 0 Transfer Format

        719
      • 21.4.3.3 CPHA = 1 Transfer Format

        721
    • 21.4.4 SPI Baud Rate Generation

      724
    • 21.4.5 Special Features

      725
      • 21.4.5.1 SS Output

        725
      • 21.4.5.2 Bidirectional Mode (MOMI or SISO)

        725
    • 21.4.6 Error Conditions

      726
      • 21.4.6.1 Mode Fault Error

        726
    • 21.4.7 Low Power Mode Options

      727
      • 21.4.7.1 SPI in Run Mode

        727
      • 21.4.7.2 SPI in Wait Mode

        727
      • 21.4.7.3 SPI in Stop Mode

        728
      • 21.4.7.4 Reset

        728
      • 21.4.7.5 Interrupts

        728
• Chapter 22 Timer Module (TIM16B6CV3)

  731
  • 22.1 Introduction

    731
    • 22.1.1 Features

      731
    • 22.1.2 Modes of Operation

      731
    • 22.1.3 Block Diagrams

      732
  • 22.2 External Signal Description

    733
    • 22.2.1 IOC5 - IOC0 - Input Capture and Output Compare Channel 5-0

      733
  • 22.3 Memory Map and Register Definition

    733
    • 22.3.1 Module Memory Map

      733
    • 22.3.2 Register Descriptions

      733
      • 22.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

        735
      • 22.3.2.2 Timer Compare Force Register (CFORC)

        735
      • 22.3.2.3 Timer Count Register (TCNT)

        736
      • 22.3.2.4 Timer System Control Register 1 (TSCR1)

        736
      • 22.3.2.5 Timer Toggle On Overflow Register 1 (TTOV)

        737
      • 22.3.2.6 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

        738
      • 22.3.2.7 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

        739
      • 22.3.2.8 Timer Interrupt Enable Register (TIE)

        740
      • 22.3.2.9 Timer System Control Register 2 (TSCR2)

        740
      • 22.3.2.10 Main Timer Interrupt Flag 1 (TFLG1)

        741
      • 22.3.2.11 Main Timer Interrupt Flag 2 (TFLG2)

        742
      • 22.3.2.12 Timer Input Capture/Output Compare Registers High and Low 0- 5(TCxH and TCxL)

        743
      • 22.3.2.13 Output Compare Pin Disconnect Register(OCPD)

        744
      • 22.3.2.14 Precision Timer Prescaler Select Register (PTPSR)

        744
  • 22.4 Functional Description

    745
    • 22.4.1 Prescaler

      746
    • 22.4.2 Input Capture

      747
    • 22.4.3 Output Compare

      747
      • 22.4.3.1 OC Channel Initialization

        747
  • 22.5 Resets

    748
  • 22.6 Interrupts

    748
    • 22.6.1 Channel [5:0] Interrupt (C[5:0]F)

      748
    • 22.6.2 Timer Overflow Interrupt (TOF)

      748
• Chapter 23 Timer Module (TIM16B8CV3)

  749
  • 23.1 Introduction

    749
    • 23.1.1 Features

      749
    • 23.1.2 Modes of Operation

      750
    • 23.1.3 Block Diagrams

      750
  • 23.2 External Signal Description

    753
    • 23.2.1 IOC7 - Input Capture and Output Compare Channel 7

      753
    • 23.2.2 IOC6 - IOC0 - Input Capture and Output Compare Channel 6-0

      753
  • 23.3 Memory Map and Register Definition

    753
    • 23.3.1 Module Memory Map

      753
    • 23.3.2 Register Descriptions

      754
      • 23.3.2.1 Timer Input Capture/Output Compare Select (TIOS)

        755
      • 23.3.2.2 Timer Compare Force Register (CFORC)

        756
      • 23.3.2.3 Output Compare 7 Mask Register (OC7M)

        756
      • 23.3.2.4 Output Compare 7 Data Register (OC7D)

        757
      • 23.3.2.5 Timer Count Register (TCNT)

        757
      • 23.3.2.6 Timer System Control Register 1 (TSCR1)

        758
      • 23.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)

        759
      • 23.3.2.8 Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)

        760
      • 23.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)

        761
      • 23.3.2.10 Timer Interrupt Enable Register (TIE)

        762
      • 23.3.2.11 Timer System Control Register 2 (TSCR2)

        763
      • 23.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)

        764
      • 23.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)

        764
      • 23.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0- 7(TCxH and TCxL)

        765
      • 23.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)

        766
      • 23.3.2.16 Pulse Accumulator Flag Register (PAFLG)

        767
      • 23.3.2.17 Pulse Accumulators Count Registers (PACNT)

        768
      • 23.3.2.18 Output Compare Pin Disconnect Register(OCPD)

        769
      • 23.3.2.19 Precision Timer Prescaler Select Register (PTPSR)

        769
  • 23.4 Functional Description

    770
    • 23.4.1 Prescaler

      772
    • 23.4.2 Input Capture

      772
    • 23.4.3 Output Compare

      772
      • 23.4.3.1 OC Channel Initialization

        773
    • 23.4.4 Pulse Accumulator

      773
    • 23.4.5 Event Counter Mode

      774
    • 23.4.6 Gated Time Accumulation Mode

      774
  • 23.5 Resets

    774
  • 23.6 Interrupts

    774
    • 23.6.1 Channel [7:0] Interrupt (C[7:0]F)

      775
    • 23.6.2 Pulse Accumulator Input Interrupt (PAOVI)

      775
    • 23.6.3 Pulse Accumulator Overflow Interrupt (PAOVF)

      775
    • 23.6.4 Timer Overflow Interrupt (TOF)

      775
• Chapter 24 16 KByte Flash Module (S12FTMRG16K1V1)

  777
  • 24.1 Introduction

    777
    • 24.1.1 Glossary

      778
    • 24.1.2 Features

      778
      • 24.1.2.1 P-Flash Features

        778
      • 24.1.2.2 EEPROM Features

        779
      • 24.1.2.3 Other Flash Module Features

        779
    • 24.1.3 Block Diagram

      779
  • 24.2 External Signal Description

    780
  • 24.3 Memory Map and Registers

    781
    • 24.3.1 Module Memory Map

      781
    • 24.3.2 Register Descriptions

      784
      • 24.3.2.1 Flash Clock Divider Register (FCLKDIV)

        786
      • 24.3.2.2 Flash Security Register (FSEC)

        787
      • 24.3.2.3 Flash CCOB Index Register (FCCOBIX)

        789
      • 24.3.2.4 Flash Reserved0 Register (FRSV0)

        789
      • 24.3.2.5 Flash Configuration Register (FCNFG)

        789
      • 24.3.2.6 Flash Error Configuration Register (FERCNFG)

        790
      • 24.3.2.7 Flash Status Register (FSTAT)

        791
      • 24.3.2.8 Flash Error Status Register (FERSTAT)

        792
      • 24.3.2.9 P-Flash Protection Register (FPROT)

        793
      • 24.3.2.10 EEPROM Protection Register (EEPROT)

        795
      • 24.3.2.11 Flash Common Command Object Register (FCCOB)

        796
      • 24.3.2.12 Flash Reserved1 Register (FRSV1)

        797
      • 24.3.2.13 Flash Reserved2 Register (FRSV2)

        798
      • 24.3.2.14 Flash Reserved3 Register (FRSV3)

        798
      • 24.3.2.15 Flash Reserved4 Register (FRSV4)

        798
      • 24.3.2.16 Flash Option Register (FOPT)

        799
      • 24.3.2.17 Flash Reserved5 Register (FRSV5)

        799
      • 24.3.2.18 Flash Reserved6 Register (FRSV6)

        799
      • 24.3.2.19 Flash Reserved7 Register (FRSV7)

        800
  • 24.4 Functional Description

    801
    • 24.4.1 Modes of Operation

      801
    • 24.4.2 IFR Version ID Word

      801
    • 24.4.3 Internal NVM resource (NVMRES)

      801
    • 24.4.4 Flash Command Operations

      801
      • 24.4.4.1 Writing the FCLKDIV Register

        801
      • 24.4.4.2 Command Write Sequence

        802
      • 24.4.4.3 Valid Flash Module Commands

        804
      • 24.4.4.4 P-Flash Commands

        804
      • 24.4.4.5 EEPROM Commands

        805
    • 24.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      806
    • 24.4.6 Flash Command Description

      807
      • 24.4.6.1 Erase Verify All Blocks Command

        807
      • 24.4.6.2 Erase Verify Block Command

        808
      • 24.4.6.3 Erase Verify P-Flash Section Command

        808
      • 24.4.6.4 Read Once Command

        809
      • 24.4.6.5 Program P-Flash Command

        810
      • 24.4.6.6 Program Once Command

        811
      • 24.4.6.7 Erase All Blocks Command

        812
      • 24.4.6.8 Erase Flash Block Command

        812
      • 24.4.6.9 Erase P-Flash Sector Command

        813
      • 24.4.6.10 Unsecure Flash Command

        814
      • 24.4.6.11 Verify Backdoor Access Key Command

        815
      • 24.4.6.12 Set User Margin Level Command

        815
      • 24.4.6.13 Set Field Margin Level Command

        817
      • 24.4.6.14 Erase Verify EEPROM Section Command

        818
      • 24.4.6.15 Program EEPROM Command

        819
      • 24.4.6.16 Erase EEPROM Sector Command

        820
    • 24.4.7 Interrupts

      821
      • 24.4.7.1 Description of Flash Interrupt Operation

        821
    • 24.4.8 Wait Mode

      822
    • 24.4.9 Stop Mode

      822
  • 24.5 Security

    822
    • 24.5.1 Unsecuring the MCU using Backdoor Key Access

      822
    • 24.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      823
    • 24.5.3 Mode and Security Effects on Flash Command Availability

      824
  • 24.6 Initialization

    824
• Chapter 25 32 KByte Flash Module (S12FTMRG32K1V1)

  825
  • 25.1 Introduction

    825
    • 25.1.1 Glossary

      826
    • 25.1.2 Features

      826
      • 25.1.2.1 P-Flash Features

        826
      • 25.1.2.2 EEPROM Features

        827
      • 25.1.2.3 Other Flash Module Features

        827
    • 25.1.3 Block Diagram

      827
  • 25.2 External Signal Description

    828
  • 25.3 Memory Map and Registers

    829
    • 25.3.1 Module Memory Map

      829
    • 25.3.2 Register Descriptions

      832
      • 25.3.2.1 Flash Clock Divider Register (FCLKDIV)

        834
      • 25.3.2.2 Flash Security Register (FSEC)

        836
      • 25.3.2.3 Flash CCOB Index Register (FCCOBIX)

        837
      • 25.3.2.4 Flash Reserved0 Register (FRSV0)

        837
      • 25.3.2.5 Flash Configuration Register (FCNFG)

        838
      • 25.3.2.6 Flash Error Configuration Register (FERCNFG)

        838
      • 25.3.2.7 Flash Status Register (FSTAT)

        839
      • 25.3.2.8 Flash Error Status Register (FERSTAT)

        840
      • 25.3.2.9 P-Flash Protection Register (FPROT)

        841
      • 25.3.2.10 EEPROM Protection Register (EEPROT)

        845
      • 25.3.2.11 Flash Common Command Object Register (FCCOB)

        847
      • 25.3.2.12 Flash Reserved1 Register (FRSV1)

        848
      • 25.3.2.13 Flash Reserved2 Register (FRSV2)

        848
      • 25.3.2.14 Flash Reserved3 Register (FRSV3)

        848
      • 25.3.2.15 Flash Reserved4 Register (FRSV4)

        849
      • 25.3.2.16 Flash Option Register (FOPT)

        849
      • 25.3.2.17 Flash Reserved5 Register (FRSV5)

        850
      • 25.3.2.18 Flash Reserved6 Register (FRSV6)

        850
      • 25.3.2.19 Flash Reserved7 Register (FRSV7)

        850
  • 25.4 Functional Description

    851
    • 25.4.1 Modes of Operation

      851
    • 25.4.2 IFR Version ID Word

      851
    • 25.4.3 Internal NVM resource (NVMRES)

      852
    • 25.4.4 Flash Command Operations

      852
      • 25.4.4.1 Writing the FCLKDIV Register

        852
      • 25.4.4.2 Command Write Sequence

        852
      • 25.4.4.3 Valid Flash Module Commands

        855
      • 25.4.4.4 P-Flash Commands

        855
      • 25.4.4.5 EEPROM Commands

        856
    • 25.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      857
    • 25.4.6 Flash Command Description

      858
      • 25.4.6.1 Erase Verify All Blocks Command

        858
      • 25.4.6.2 Erase Verify Block Command

        859
      • 25.4.6.3 Erase Verify P-Flash Section Command

        859
      • 25.4.6.4 Read Once Command

        860
      • 25.4.6.5 Program P-Flash Command

        861
      • 25.4.6.6 Program Once Command

        862
      • 25.4.6.7 Erase All Blocks Command

        863
      • 25.4.6.8 Erase Flash Block Command

        863
      • 25.4.6.9 Erase P-Flash Sector Command

        864
      • 25.4.6.10 Unsecure Flash Command

        865
      • 25.4.6.11 Verify Backdoor Access Key Command

        865
      • 25.4.6.12 Set User Margin Level Command

        866
      • 25.4.6.13 Set Field Margin Level Command

        868
      • 25.4.6.14 Erase Verify EEPROM Section Command

        869
      • 25.4.6.15 Program EEPROM Command

        870
      • 25.4.6.16 Erase EEPROM Sector Command

        871
    • 25.4.7 Interrupts

      872
      • 25.4.7.1 Description of Flash Interrupt Operation

        872
    • 25.4.8 Wait Mode

      873
    • 25.4.9 Stop Mode

      873
  • 25.5 Security

    873
    • 25.5.1 Unsecuring the MCU using Backdoor Key Access

      873
    • 25.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      874
    • 25.5.3 Mode and Security Effects on Flash Command Availability

      875
  • 25.6 Initialization

    875
• Chapter 26 48 KByte Flash Module (S12FTMRG48K1V1)

  877
  • 26.1 Introduction

    877
    • 26.1.1 Glossary

      878
    • 26.1.2 Features

      878
      • 26.1.2.1 P-Flash Features

        878
      • 26.1.2.2 EEPROM Features

        879
      • 26.1.2.3 Other Flash Module Features

        879
    • 26.1.3 Block Diagram

      880
  • 26.2 External Signal Description

    880
  • 26.3 Memory Map and Registers

    881
    • 26.3.1 Module Memory Map

      881
    • 26.3.2 Register Descriptions

      885
      • 26.3.2.1 Flash Clock Divider Register (FCLKDIV)

        887
      • 26.3.2.2 Flash Security Register (FSEC)

        889
      • 26.3.2.3 Flash CCOB Index Register (FCCOBIX)

        890
      • 26.3.2.4 Flash Reserved0 Register (FRSV0)

        890
      • 26.3.2.5 Flash Configuration Register (FCNFG)

        891
      • 26.3.2.6 Flash Error Configuration Register (FERCNFG)

        891
      • 26.3.2.7 Flash Status Register (FSTAT)

        892
      • 26.3.2.8 Flash Error Status Register (FERSTAT)

        893
      • 26.3.2.9 P-Flash Protection Register (FPROT)

        894
      • 26.3.2.10 EEPROM Protection Register (EEPROT)

        898
      • 26.3.2.11 Flash Common Command Object Register (FCCOB)

        900
      • 26.3.2.12 Flash Reserved1 Register (FRSV1)

        901
      • 26.3.2.13 Flash Reserved2 Register (FRSV2)

        901
      • 26.3.2.14 Flash Reserved3 Register (FRSV3)

        901
      • 26.3.2.15 Flash Reserved4 Register (FRSV4)

        902
      • 26.3.2.16 Flash Option Register (FOPT)

        902
      • 26.3.2.17 Flash Reserved5 Register (FRSV5)

        903
      • 26.3.2.18 Flash Reserved6 Register (FRSV6)

        903
      • 26.3.2.19 Flash Reserved7 Register (FRSV7)

        903
  • 26.4 Functional Description

    904
    • 26.4.1 Modes of Operation

      904
    • 26.4.2 IFR Version ID Word

      904
    • 26.4.3 Internal NVM resource (NVMRES)

      905
    • 26.4.4 Flash Command Operations

      905
      • 26.4.4.1 Writing the FCLKDIV Register

        905
      • 26.4.4.2 Command Write Sequence

        905
      • 26.4.4.3 Valid Flash Module Commands

        908
      • 26.4.4.4 P-Flash Commands

        908
      • 26.4.4.5 EEPROM Commands

        909
    • 26.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      910
    • 26.4.6 Flash Command Description

      911
      • 26.4.6.1 Erase Verify All Blocks Command

        911
      • 26.4.6.2 Erase Verify Block Command

        912
      • 26.4.6.3 Erase Verify P-Flash Section Command

        912
      • 26.4.6.4 Read Once Command

        913
      • 26.4.6.5 Program P-Flash Command

        914
      • 26.4.6.6 Program Once Command

        915
      • 26.4.6.7 Erase All Blocks Command

        916
      • 26.4.6.8 Erase Flash Block Command

        916
      • 26.4.6.9 Erase P-Flash Sector Command

        917
      • 26.4.6.10 Unsecure Flash Command

        918
      • 26.4.6.11 Verify Backdoor Access Key Command

        918
      • 26.4.6.12 Set User Margin Level Command

        919
      • 26.4.6.13 Set Field Margin Level Command

        921
      • 26.4.6.14 Erase Verify EEPROM Section Command

        922
      • 26.4.6.15 Program EEPROM Command

        923
      • 26.4.6.16 Erase EEPROM Sector Command

        924
    • 26.4.7 Interrupts

      925
      • 26.4.7.1 Description of Flash Interrupt Operation

        925
    • 26.4.8 Wait Mode

      926
    • 26.4.9 Stop Mode

      926
  • 26.5 Security

    926
    • 26.5.1 Unsecuring the MCU using Backdoor Key Access

      926
    • 26.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      927
    • 26.5.3 Mode and Security Effects on Flash Command Availability

      928
  • 26.6 Initialization

    928
• Chapter 27 64 KByte Flash Module (S12FTMRG64K1V1)

  929
  • 27.1 Introduction

    929
    • 27.1.1 Glossary

      930
    • 27.1.2 Features

      930
      • 27.1.2.1 P-Flash Features

        930
      • 27.1.2.2 EEPROM Features

        931
      • 27.1.2.3 Other Flash Module Features

        931
    • 27.1.3 Block Diagram

      931
  • 27.2 External Signal Description

    932
  • 27.3 Memory Map and Registers

    933
    • 27.3.1 Module Memory Map

      933
    • 27.3.2 Register Descriptions

      936
      • 27.3.2.1 Flash Clock Divider Register (FCLKDIV)

        938
      • 27.3.2.2 Flash Security Register (FSEC)

        940
      • 27.3.2.3 Flash CCOB Index Register (FCCOBIX)

        941
      • 27.3.2.4 Flash Reserved0 Register (FRSV0)

        941
      • 27.3.2.5 Flash Configuration Register (FCNFG)

        942
      • 27.3.2.6 Flash Error Configuration Register (FERCNFG)

        942
      • 27.3.2.7 Flash Status Register (FSTAT)

        943
      • 27.3.2.8 Flash Error Status Register (FERSTAT)

        944
      • 27.3.2.9 P-Flash Protection Register (FPROT)

        945
      • 27.3.2.10 EEPROM Protection Register (EEPROT)

        949
      • 27.3.2.11 Flash Common Command Object Register (FCCOB)

        951
      • 27.3.2.12 Flash Reserved1 Register (FRSV1)

        952
      • 27.3.2.13 Flash Reserved2 Register (FRSV2)

        952
      • 27.3.2.14 Flash Reserved3 Register (FRSV3)

        952
      • 27.3.2.15 Flash Reserved4 Register (FRSV4)

        953
      • 27.3.2.16 Flash Option Register (FOPT)

        953
      • 27.3.2.17 Flash Reserved5 Register (FRSV5)

        954
      • 27.3.2.18 Flash Reserved6 Register (FRSV6)

        954
      • 27.3.2.19 Flash Reserved7 Register (FRSV7)

        954
  • 27.4 Functional Description

    955
    • 27.4.1 Modes of Operation

      955
    • 27.4.2 IFR Version ID Word

      955
    • 27.4.3 Internal NVM resource (NVMRES)

      956
    • 27.4.4 Flash Command Operations

      956
      • 27.4.4.1 Writing the FCLKDIV Register

        956
      • 27.4.4.2 Command Write Sequence

        956
      • 27.4.4.3 Valid Flash Module Commands

        959
      • 27.4.4.4 P-Flash Commands

        959
      • 27.4.4.5 EEPROM Commands

        960
    • 27.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      961
    • 27.4.6 Flash Command Description

      962
      • 27.4.6.1 Erase Verify All Blocks Command

        962
      • 27.4.6.2 Erase Verify Block Command

        963
      • 27.4.6.3 Erase Verify P-Flash Section Command

        963
      • 27.4.6.4 Read Once Command

        964
      • 27.4.6.5 Program P-Flash Command

        965
      • 27.4.6.6 Program Once Command

        966
      • 27.4.6.7 Erase All Blocks Command

        967
      • 27.4.6.8 Erase Flash Block Command

        967
      • 27.4.6.9 Erase P-Flash Sector Command

        968
      • 27.4.6.10 Unsecure Flash Command

        969
      • 27.4.6.11 Verify Backdoor Access Key Command

        969
      • 27.4.6.12 Set User Margin Level Command

        970
      • 27.4.6.13 Set Field Margin Level Command

        972
      • 27.4.6.14 Erase Verify EEPROM Section Command

        973
      • 27.4.6.15 Program EEPROM Command

        974
      • 27.4.6.16 Erase EEPROM Sector Command

        975
    • 27.4.7 Interrupts

      976
      • 27.4.7.1 Description of Flash Interrupt Operation

        976
    • 27.4.8 Wait Mode

      977
    • 27.4.9 Stop Mode

      977
  • 27.5 Security

    977
    • 27.5.1 Unsecuring the MCU using Backdoor Key Access

      977
    • 27.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      978
    • 27.5.3 Mode and Security Effects on Flash Command Availability

      979
  • 27.6 Initialization

    979
• Chapter 28 96 KByte Flash Module (S12FTMRG96K1V1)

  981
  • 28.1 Introduction

    981
    • 28.1.1 Glossary

      982
    • 28.1.2 Features

      982
      • 28.1.2.1 P-Flash Features

        982
      • 28.1.2.2 EEPROM Features

        983
      • 28.1.2.3 Other Flash Module Features

        983
    • 28.1.3 Block Diagram

      983
  • 28.2 External Signal Description

    984
  • 28.3 Memory Map and Registers

    985
    • 28.3.1 Module Memory Map

      985
    • 28.3.2 Register Descriptions

      988
      • 28.3.2.1 Flash Clock Divider Register (FCLKDIV)

        990
      • 28.3.2.2 Flash Security Register (FSEC)

        992
      • 28.3.2.3 Flash CCOB Index Register (FCCOBIX)

        993
      • 28.3.2.4 Flash Reserved0 Register (FRSV0)

        993
      • 28.3.2.5 Flash Configuration Register (FCNFG)

        994
      • 28.3.2.6 Flash Error Configuration Register (FERCNFG)

        994
      • 28.3.2.7 Flash Status Register (FSTAT)

        995
      • 28.3.2.8 Flash Error Status Register (FERSTAT)

        996
      • 28.3.2.9 P-Flash Protection Register (FPROT)

        997
      • 28.3.2.10 EEPROM Protection Register (EEPROT)

        1001
      • 28.3.2.11 Flash Common Command Object Register (FCCOB)

        1003
      • 28.3.2.12 Flash Reserved1 Register (FRSV1)

        1004
      • 28.3.2.13 Flash Reserved2 Register (FRSV2)

        1004
      • 28.3.2.14 Flash Reserved3 Register (FRSV3)

        1004
      • 28.3.2.15 Flash Reserved4 Register (FRSV4)

        1005
      • 28.3.2.16 Flash Option Register (FOPT)

        1005
      • 28.3.2.17 Flash Reserved5 Register (FRSV5)

        1006
      • 28.3.2.18 Flash Reserved6 Register (FRSV6)

        1006
      • 28.3.2.19 Flash Reserved7 Register (FRSV7)

        1006
  • 28.4 Functional Description

    1007
    • 28.4.1 Modes of Operation

      1007
    • 28.4.2 IFR Version ID Word

      1007
    • 28.4.3 Internal NVM resource (NVMRES)

      1008
    • 28.4.4 Flash Command Operations

      1008
      • 28.4.4.1 Writing the FCLKDIV Register

        1008
      • 28.4.4.2 Command Write Sequence

        1008
      • 28.4.4.3 Valid Flash Module Commands

        1011
      • 28.4.4.4 P-Flash Commands

        1011
      • 28.4.4.5 EEPROM Commands

        1012
    • 28.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      1013
    • 28.4.6 Flash Command Description

      1014
      • 28.4.6.1 Erase Verify All Blocks Command

        1014
      • 28.4.6.2 Erase Verify Block Command

        1015
      • 28.4.6.3 Erase Verify P-Flash Section Command

        1016
      • 28.4.6.4 Read Once Command

        1016
      • 28.4.6.5 Program P-Flash Command

        1017
      • 28.4.6.6 Program Once Command

        1018
      • 28.4.6.7 Erase All Blocks Command

        1019
      • 28.4.6.8 Erase Flash Block Command

        1020
      • 28.4.6.9 Erase P-Flash Sector Command

        1020
      • 28.4.6.10 Unsecure Flash Command

        1021
      • 28.4.6.11 Verify Backdoor Access Key Command

        1022
      • 28.4.6.12 Set User Margin Level Command

        1022
      • 28.4.6.13 Set Field Margin Level Command

        1024
      • 28.4.6.14 Erase Verify EEPROM Section Command

        1025
      • 28.4.6.15 Program EEPROM Command

        1026
      • 28.4.6.16 Erase EEPROM Sector Command

        1027
    • 28.4.7 Interrupts

      1028
      • 28.4.7.1 Description of Flash Interrupt Operation

        1028
    • 28.4.8 Wait Mode

      1029
    • 28.4.9 Stop Mode

      1029
  • 28.5 Security

    1029
    • 28.5.1 Unsecuring the MCU using Backdoor Key Access

      1029
    • 28.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      1030
    • 28.5.3 Mode and Security Effects on Flash Command Availability

      1031
  • 28.6 Initialization

    1031
• Chapter 29 128 KByte Flash Module (S12FTMRG128K1V1)

  1033
  • 29.1 Introduction

    1033
    • 29.1.1 Glossary

      1034
    • 29.1.2 Features

      1034
      • 29.1.2.1 P-Flash Features

        1034
      • 29.1.2.2 EEPROM Features

        1035
      • 29.1.2.3 Other Flash Module Features

        1035
    • 29.1.3 Block Diagram

      1035
  • 29.2 External Signal Description

    1036
  • 29.3 Memory Map and Registers

    1037
    • 29.3.1 Module Memory Map

      1037
    • 29.3.2 Register Descriptions

      1041
      • 29.3.2.1 Flash Clock Divider Register (FCLKDIV)

        1042
      • 29.3.2.2 Flash Security Register (FSEC)

        1044
      • 29.3.2.3 Flash CCOB Index Register (FCCOBIX)

        1045
      • 29.3.2.4 Flash Reserved0 Register (FRSV0)

        1046
      • 29.3.2.5 Flash Configuration Register (FCNFG)

        1046
      • 29.3.2.6 Flash Error Configuration Register (FERCNFG)

        1047
      • 29.3.2.7 Flash Status Register (FSTAT)

        1048
      • 29.3.2.8 Flash Error Status Register (FERSTAT)

        1049
      • 29.3.2.9 P-Flash Protection Register (FPROT)

        1050
      • 29.3.2.10 EEPROM Protection Register (DFPROT)

        1053
      • 29.3.2.11 Flash Common Command Object Register (FCCOB)

        1055
      • 29.3.2.12 Flash Reserved1 Register (FRSV1)

        1056
      • 29.3.2.13 Flash Reserved2 Register (FRSV2)

        1056
      • 29.3.2.14 Flash Reserved3 Register (FRSV3)

        1056
      • 29.3.2.15 Flash Reserved4 Register (FRSV4)

        1057
      • 29.3.2.16 Flash Option Register (FOPT)

        1057
      • 29.3.2.17 Flash Reserved5 Register (FRSV5)

        1058
      • 29.3.2.18 Flash Reserved6 Register (FRSV6)

        1058
      • 29.3.2.19 Flash Reserved7 Register (FRSV7)

        1058
  • 29.4 Functional Description

    1059
    • 29.4.1 Modes of Operation

      1059
    • 29.4.2 IFR Version ID Word

      1059
    • 29.4.3 Internal NVM resource (NVMRES)

      1060
    • 29.4.4 Flash Command Operations

      1060
      • 29.4.4.1 Writing the FCLKDIV Register

        1060
      • 29.4.4.2 Command Write Sequence

        1060
      • 29.4.4.3 Valid Flash Module Commands

        1063
      • 29.4.4.4 P-Flash Commands

        1063
      • 29.4.4.5 EEPROM Commands

        1064
    • 29.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      1065
    • 29.4.6 Flash Command Description

      1066
      • 29.4.6.1 Erase Verify All Blocks Command

        1066
      • 29.4.6.2 Erase Verify Block Command

        1067
      • 29.4.6.3 Erase Verify P-Flash Section Command

        1067
      • 29.4.6.4 Read Once Command

        1068
      • 29.4.6.5 Program P-Flash Command

        1069
      • 29.4.6.6 Program Once Command

        1070
      • 29.4.6.7 Erase All Blocks Command

        1071
      • 29.4.6.8 Erase Flash Block Command

        1071
      • 29.4.6.9 Erase P-Flash Sector Command

        1072
      • 29.4.6.10 Unsecure Flash Command

        1073
      • 29.4.6.11 Verify Backdoor Access Key Command

        1073
      • 29.4.6.12 Set User Margin Level Command

        1074
      • 29.4.6.13 Set Field Margin Level Command

        1076
      • 29.4.6.14 Erase Verify EEPROM Section Command

        1077
      • 29.4.6.15 Program EEPROM Command

        1078
      • 29.4.6.16 Erase EEPROM Sector Command

        1079
    • 29.4.7 Interrupts

      1080
      • 29.4.7.1 Description of Flash Interrupt Operation

        1080
    • 29.4.8 Wait Mode

      1081
    • 29.4.9 Stop Mode

      1081
  • 29.5 Security

    1081
    • 29.5.1 Unsecuring the MCU using Backdoor Key Access

      1081
    • 29.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      1082
    • 29.5.3 Mode and Security Effects on Flash Command Availability

      1083
  • 29.6 Initialization

    1083
• Chapter 30 192 KByte Flash Module (S12FTMRG192K2V1)

  1085
  • 30.1 Introduction

    1085
    • 30.1.1 Glossary

      1086
    • 30.1.2 Features

      1086
      • 30.1.2.1 P-Flash Features

        1086
      • 30.1.2.2 EEPROM Features

        1087
      • 30.1.2.3 Other Flash Module Features

        1087
    • 30.1.3 Block Diagram

      1087
  • 30.2 External Signal Description

    1088
  • 30.3 Memory Map and Registers

    1089
    • 30.3.1 Module Memory Map

      1089
    • 30.3.2 Register Descriptions

      1093
      • 30.3.2.1 Flash Clock Divider Register (FCLKDIV)

        1094
      • 30.3.2.2 Flash Security Register (FSEC)

        1096
      • 30.3.2.3 Flash CCOB Index Register (FCCOBIX)

        1097
      • 30.3.2.4 Flash Reserved0 Register (FRSV0)

        1098
      • 30.3.2.5 Flash Configuration Register (FCNFG)

        1098
      • 30.3.2.6 Flash Error Configuration Register (FERCNFG)

        1099
      • 30.3.2.7 Flash Status Register (FSTAT)

        1100
      • 30.3.2.8 Flash Error Status Register (FERSTAT)

        1101
      • 30.3.2.9 P-Flash Protection Register (FPROT)

        1102
      • 30.3.2.10 EEPROM Protection Register (EEPROT)

        1105
      • 30.3.2.11 Flash Common Command Object Register (FCCOB)

        1107
      • 30.3.2.12 Flash Reserved1 Register (FRSV1)

        1108
      • 30.3.2.13 Flash Reserved2 Register (FRSV2)

        1108
      • 30.3.2.14 Flash Reserved3 Register (FRSV3)

        1108
      • 30.3.2.15 Flash Reserved4 Register (FRSV4)

        1109
      • 30.3.2.16 Flash Option Register (FOPT)

        1109
      • 30.3.2.17 Flash Reserved5 Register (FRSV5)

        1110
      • 30.3.2.18 Flash Reserved6 Register (FRSV6)

        1110
      • 30.3.2.19 Flash Reserved7 Register (FRSV7)

        1110
  • 30.4 Functional Description

    1111
    • 30.4.1 Modes of Operation

      1111
    • 30.4.2 IFR Version ID Word

      1111
    • 30.4.3 Internal NVM resource (NVMRES)

      1112
    • 30.4.4 Flash Command Operations

      1112
      • 30.4.4.1 Writing the FCLKDIV Register

        1112
      • 30.4.4.2 Command Write Sequence

        1112
      • 30.4.4.3 Valid Flash Module Commands

        1115
      • 30.4.4.4 P-Flash Commands

        1115
      • 30.4.4.5 EEPROM Commands

        1116
    • 30.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      1117
    • 30.4.6 Flash Command Description

      1118
      • 30.4.6.1 Erase Verify All Blocks Command

        1118
      • 30.4.6.2 Erase Verify Block Command

        1119
      • 30.4.6.3 Erase Verify P-Flash Section Command

        1119
      • 30.4.6.4 Read Once Command

        1120
      • 30.4.6.5 Program P-Flash Command

        1121
      • 30.4.6.6 Program Once Command

        1122
      • 30.4.6.7 Erase All Blocks Command

        1123
      • 30.4.6.8 Erase Flash Block Command

        1123
      • 30.4.6.9 Erase P-Flash Sector Command

        1124
      • 30.4.6.10 Unsecure Flash Command

        1125
      • 30.4.6.11 Verify Backdoor Access Key Command

        1125
      • 30.4.6.12 Set User Margin Level Command

        1126
      • 30.4.6.13 Set Field Margin Level Command

        1127
      • 30.4.6.14 Erase Verify EEPROM Section Command

        1129
      • 30.4.6.15 Program EEPROM Command

        1130
      • 30.4.6.16 Erase EEPROM Sector Command

        1130
    • 30.4.7 Interrupts

      1131
      • 30.4.7.1 Description of Flash Interrupt Operation

        1132
    • 30.4.8 Wait Mode

      1132
    • 30.4.9 Stop Mode

      1132
  • 30.5 Security

    1133
    • 30.5.1 Unsecuring the MCU using Backdoor Key Access

      1133
    • 30.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      1134
    • 30.5.3 Mode and Security Effects on Flash Command Availability

      1134
  • 30.6 Initialization

    1134
• Chapter 31 240 KByte Flash Module (S12FTMRG240K2V1)

  1137
  • 31.1 Introduction

    1137
    • 31.1.1 Glossary

      1138
    • 31.1.2 Features

      1138
      • 31.1.2.1 P-Flash Features

        1138
      • 31.1.2.2 EEPROM Features

        1139
      • 31.1.2.3 Other Flash Module Features

        1139
    • 31.1.3 Block Diagram

      1139
  • 31.2 External Signal Description

    1140
  • 31.3 Memory Map and Registers

    1141
    • 31.3.1 Module Memory Map

      1141
    • 31.3.2 Register Descriptions

      1145
      • 31.3.2.1 Flash Clock Divider Register (FCLKDIV)

        1146
      • 31.3.2.2 Flash Security Register (FSEC)

        1148
      • 31.3.2.3 Flash CCOB Index Register (FCCOBIX)

        1149
      • 31.3.2.4 Flash Reserved0 Register (FRSV0)

        1150
      • 31.3.2.5 Flash Configuration Register (FCNFG)

        1150
      • 31.3.2.6 Flash Error Configuration Register (FERCNFG)

        1151
      • 31.3.2.7 Flash Status Register (FSTAT)

        1152
      • 31.3.2.8 Flash Error Status Register (FERSTAT)

        1153
      • 31.3.2.9 P-Flash Protection Register (FPROT)

        1154
      • 31.3.2.10 EEPROM Protection Register (EEPROT)

        1157
      • 31.3.2.11 Flash Common Command Object Register (FCCOB)

        1159
      • 31.3.2.12 Flash Reserved1 Register (FRSV1)

        1160
      • 31.3.2.13 Flash Reserved2 Register (FRSV2)

        1160
      • 31.3.2.14 Flash Reserved3 Register (FRSV3)

        1160
      • 31.3.2.15 Flash Reserved4 Register (FRSV4)

        1161
      • 31.3.2.16 Flash Option Register (FOPT)

        1161
      • 31.3.2.17 Flash Reserved5 Register (FRSV5)

        1162
      • 31.3.2.18 Flash Reserved6 Register (FRSV6)

        1162
      • 31.3.2.19 Flash Reserved7 Register (FRSV7)

        1162
  • 31.4 Functional Description

    1163
    • 31.4.1 Modes of Operation

      1163
    • 31.4.2 IFR Version ID Word

      1163
    • 31.4.3 Internal NVM resource (NVMRES)

      1164
    • 31.4.4 Flash Command Operations

      1164
      • 31.4.4.1 Writing the FCLKDIV Register

        1164
      • 31.4.4.2 Command Write Sequence

        1164
      • 31.4.4.3 Valid Flash Module Commands

        1167
      • 31.4.4.4 P-Flash Commands

        1167
      • 31.4.4.5 EEPROM Commands

        1168
    • 31.4.5 Allowed Simultaneous P-Flash and EEPROM Operations

      1169
    • 31.4.6 Flash Command Description

      1170
      • 31.4.6.1 Erase Verify All Blocks Command

        1170
      • 31.4.6.2 Erase Verify Block Command

        1171
      • 31.4.6.3 Erase Verify P-Flash Section Command

        1171
      • 31.4.6.4 Read Once Command

        1172
      • 31.4.6.5 Program P-Flash Command

        1173
      • 31.4.6.6 Program Once Command

        1174
      • 31.4.6.7 Erase All Blocks Command

        1175
      • 31.4.6.8 Erase Flash Block Command

        1175
      • 31.4.6.9 Erase P-Flash Sector Command

        1176
      • 31.4.6.10 Unsecure Flash Command

        1177
      • 31.4.6.11 Verify Backdoor Access Key Command

        1177
      • 31.4.6.12 Set User Margin Level Command

        1178
      • 31.4.6.13 Set Field Margin Level Command

        1179
      • 31.4.6.14 Erase Verify EEPROM Section Command

        1181
      • 31.4.6.15 Program EEPROM Command

        1182
      • 31.4.6.16 Erase EEPROM Sector Command

        1182
    • 31.4.7 Interrupts

      1183
      • 31.4.7.1 Description of Flash Interrupt Operation

        1184
    • 31.4.8 Wait Mode

      1184
    • 31.4.9 Stop Mode

      1184
  • 31.5 Security

    1185
    • 31.5.1 Unsecuring the MCU using Backdoor Key Access

      1185
    • 31.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM

      1186
    • 31.5.3 Mode and Security Effects on Flash Command Availability

      1186
  • 31.6 Initialization

    1186
• Appendix A Electrical Characteristics

  1189
  • A.1 General

    1190
    • A.1.1 Parameter Classification

      1190
    • A.1.2 Power Supply

      1190
    • A.1.3 Pins

      1191
      • A.1.3.1 I/O Pins

        1191
      • A.1.3.2 Analog Reference

        1191
      • A.1.3.3 Oscillator

        1191
      • A.1.3.4 TEST

        1191
    • A.1.4 Current Injection

      1191
    • A.1.5 Absolute Maximum Ratings

      1192
    • A.1.6 ESD Protection and Latch-up Immunity

      1192
    • A.1.7 Operating Conditions

      1193
    • A.1.8 Power Dissipation and Thermal Characteristics

      1195
  • A.2 I/O Characteristics

    1199
  • A.3 Supply Currents

    1203
    • A.3.1 Measurement Conditions

      1203
  • A.4 ADC Characteristics

    1208
    • A.4.1 ADC Operating Characteristics

      1208
    • A.4.2 Factors Influencing Accuracy

      1209
      • A.4.2.1 Differential Reference Voltage

        1209
      • A.4.2.2 Port AD Output Drivers Switching

        1209
      • A.4.2.3 Source Resistance

        1209
      • A.4.2.4 Source Capacitance

        1210
      • A.4.2.5 Current Injection

        1210
    • A.4.3 ADC Accuracy

      1210
      • A.4.3.1 ADC Accuracy Definitions

        1211
      • A.4.3.2 ADC Analog Input Parasitics

        1220
    • A.4.4 ADC Temperature Sensor

      1220
  • A.5 ACMP Characteristics

    1220
  • A.6 DAC Characteristics

    1222
  • A.7 NVM

    1223
    • A.7.1 Timing Parameters

      1223
      • A.7.1.1 Erase Verify All Blocks (Blank Check) (FCMD=0x01)

        1224
      • A.7.1.2 Erase Verify Block (Blank Check) (FCMD=0x02)

        1224
      • A.7.1.3 Erase Verify P-Flash Section (FCMD=0x03)

        1225
      • A.7.1.4 Read Once (FCMD=0x04)

        1225
      • A.7.1.5 Program P-Flash (FCMD=0x06)

        1226
      • A.7.1.6 Program Once (FCMD=0x07)

        1226
      • A.7.1.7 Erase All Blocks (FCMD=0x08)

        1226
      • A.7.1.8 Erase P-Flash Block (FCMD=0x09)

        1227
      • A.7.1.9 Erase P-Flash Sector (FCMD=0x0A)

        1227
      • A.7.1.10 Unsecure Flash (FCMD=0x0B)

        1227
      • A.7.1.11 Verify Backdoor Access Key (FCMD=0x0C)

        1228
      • A.7.1.12 Set User Margin Level (FCMD=0x0D)

        1228
      • A.7.1.13 Set Field Margin Level (FCMD=0x0E)

        1228
      • A.7.1.14 Erase Verify EEPROM Section (FCMD=0x10)

        1228
      • A.7.1.15 Program EEPROM (FCMD=0x11)

        1229
      • A.7.1.16 Erase EEPROM Sector (FCMD=0x12)

        1229
    • A.7.2 NVM Reliability Parameters

      1231
  • A.8 Phase Locked Loop

    1232
    • A.8.1 Jitter Definitions

      1232
    • A.8.2 Electrical Characteristics for the PLL

      1234
  • A.9 Electrical Characteristics for the IRC1M

    1234
  • A.10 Electrical Characteristics for the Oscillator (XOSCLCP)

    1236
  • A.11 Reset Characteristics

    1237
  • A.12 Electrical Specification for Voltage Regulator

    1238
  • A.13 Chip Power-up and Voltage Drops

    1240
  • A.14 MSCAN

    1240
  • A.15 SPI Timing

    1241
    • A.15.1 Master Mode

      1241
    • A.15.2 Slave Mode

      1243
  • A.16 ADC Conversion Result Reference

    1245
• Appendix B Detailed Register Address Map

  1247
  • B.1 Detailed Register Map

    1247
• Appendix C Ordering and Shipping Information

  1267
  • C.1 Ordering Information

    1267
• Appendix D Package and Die Information

  1269
  • D.1 100 LQFP Mechanical Dimensions

    1270
  • D.2 64 LQFP Mechanical Dimensions

    1273
  • D.3 48 LQFP Mechanical Dimensions

    1276
  • D.4 48 QFN Mechanical Dimensions

    1278
  • D.5 32 LQFP Mechanical Dimensions

    1281
  • D.6 20 TSSOP Mechanical Dimensions

    1284
  • D.7 KGD Information

    1287