Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados

Freescale Semiconductor

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If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied
to the CPU will default to that of the spurious interrupt vector.

Care must be taken to ensure that all interrupt requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0080)).

The INT module supports three system reset exception request types (please refer to the Clock and Reset
generator module for details):

1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)

2. Clock monitor reset request

3. COP watchdog reset request

The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon
request by the CPU is shown in

.

1

16 bits vector address based

0xFFFE

Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)

0xFFFC

Clock monitor reset

0xFFFA

COP watchdog reset

(Vector base + 0x00F8)

Unimplemented opcode trap

(Vector base + 0x00F6)

Software interrupt instruction (SWI) or BDM vector request

(Vector base + 0x00F4)

X bit maskable interrupt request (XIRQ or D2D error interrupt)

2

2

D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt

(Vector base + 0x00F2)

IRQ or D2D interrupt request

3

3

D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt

(Vector base + 0x00F0–0x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the

vector address, in descending order)

(Vector base + 0x0080)

Spurious interrupt