Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados
Códigos do produto
TWR-S12G240
S12S Debug Module (S12SDBGV2)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
335
8.4.2.1.2
Comparator B
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in
shown in
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in
Comparator C in
.
8.4.2.1.3
Comparator A
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
lists access considerations with data bus comparison. On word accesses the data byte of the
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in
Comparator A in the same way as described for Comparator C in
Table 8-34. Comparator A Matches When Accessing ADDR[n]
Table 8-32. Comparator C Access Considerations
Condition For Valid Match
Comp C Address
RWE
RW
Examples
Read and write accesses of ADDR[n]
ADDR[n]
1
1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
The comparator address register must contain the exact address from the code.
0
X
LDAA ADDR[n]
STAA #$BYTE ADDR[n]
Write accesses of ADDR[n]
ADDR[n]
1
0
STAA #$BYTE ADDR[n]
Read accesses of ADDR[n]
ADDR[n]
1
1
LDAA #$BYTE ADDR[n]
Table 8-33. Comparator B Access Size Considerations
Condition For Valid Match
Comp B Address
RWE
SZE
SZ8
Examples
Word and byte accesses of ADDR[n]
ADDR[n]
1
1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
The comparator address register must contain the exact address from the code.
0
0
X
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word accesses of ADDR[n] only
ADDR[n]
0
1
0
MOVW #$WORD ADDR[n]
LDD ADDR[n]
Byte accesses of ADDR[n] only
ADDR[n]
0
1
1
MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
SZE
SZ
DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL
Comment
0
X
$0000
Byte
Word
Word
No databus comparison