Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados
Códigos do produto
TWR-S12G240
Serial Communication Interface (S12SCIV5)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
679
20.3.2.8
SCI Status Register 2 (SCISR2)
Read: Anytime
Write: Anytime
1
FE
Framing Error Flag — FE is set when a logic 0 is accepted as the stop bit. FE bit is set during the same cycle
as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
as the RDRF flag but does not get set in the case of an overrun. FE inhibits further data reception until it is
cleared. Clear FE by reading SCI status register 1 (SCISR1) with FE set and then reading the SCI data register
low (SCIDRL).
0 No framing error
1 Framing error
0
PF
Parity Error Flag — PF is set when the parity enable bit (PE) is set and the parity of the received data does not
match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
match the parity type bit (PT). PF bit is set during the same cycle as the RDRF flag but does not get set in the
case of an overrun. Clear PF by reading SCI status register 1 (SCISR1), and then reading SCI data register low
(SCIDRL).
0 No parity error
1 Parity error
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
AMAP
0
0
TXPOL
RXPOL
BRK13
TXDIR
RAF
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-11. SCI Status Register 2 (SCISR2)
Table 20-12. SCISR2 Field Descriptions
Field
Description
7
AMAP
Alternative Map — This bit controls which registers sharing the same address space are accessible. In the reset
condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and
status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible
condition the SCI behaves as previous versions. Setting AMAP=1 allows the access to another set of control and
status registers and hides the baud rate and SCI control Register 1.
0 The registers labelled SCIBDH (0x0000),SCIBDL (0x0001), SCICR1 (0x0002) are accessible
1 The registers labelled SCIASR1 (0x0000),SCIACR1 (0x0001), SCIACR2 (0x00002) are accessible
4
TXPOL
Transmit Polarity — This bit control the polarity of the transmitted data. In NRZ format, a one is represented by
a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
a mark and a zero is represented by a space for normal polarity, and the opposite for inverted polarity. In IrDA
format, a zero is represented by short high pulse in the middle of a bit time remaining idle low for a one for normal
polarity, and a zero is represented by short low pulse in the middle of a bit time remaining idle high for a one for
inverted polarity.
0 Normal polarity
1 Inverted polarity
Table 20-11. SCISR1 Field Descriptions (continued)
Field
Description