Freescale Semiconductor Tower System Module S12G240 TWR-S12G240 TWR-S12G240 Ficha De Dados
Códigos do produto
TWR-S12G240
Serial Communication Interface (S12SCIV5)
MC9S12G Family Reference Manual,
Rev.1.23
700
Freescale Semiconductor
NOTE
In single-wire operation data from the TXD pin is inverted if RXPOL is set.
20.4.8
Loop Operation
In loop operation the transmitter output goes to the receiver input. The RXD pin is disconnected from the
SCI.
SCI.
Figure 20-31. Loop Operation (LOOPS = 1, RSRC = 0)
Enable loop operation by setting the LOOPS bit and clearing the RSRC bit in SCI control register 1
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).
(SCICR1). Setting the LOOPS bit disables the path from the RXD pin to the receiver. Clearing the RSRC
bit connects the transmitter output to the receiver input. Both the transmitter and receiver must be enabled
(TE = 1 and RE = 1).
NOTE
In loop operation data from the transmitter is not recognized by the receiver
if RXPOL and TXPOL are not the same.
if RXPOL and TXPOL are not the same.
20.5
Initialization/Application Information
20.5.1
Reset Initialization
See
.
20.5.2
Modes of Operation
20.5.2.1
Run Mode
Normal mode of operation.
To initialize a SCI transmission, see
.
20.5.2.2
Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
(SCICR1).
•
If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
•
If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
RXD
Transmitter
Receiver
TXD