Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB Manual Do Utilizador

19-8

Freescale Semiconductor

 

of IMMRBAR together with the SPI block base address and offset listed in 

. Undefined 4-byte 

address spaces within offset 0x000–0xFFF are reserved.

This section describes the registers listed in 

. 

SPMODE, shown in 

, controls both the SPI operation mode and clock source.

0x000–0x01F

Reserved

—

—

—

0x020

SPI mode register (SPMODE)

R/W

0x0000_0000

0x024

SPI event register (SPIE)

Mixed

0x0000_0000

0x028

SPI mask register (SPIM)

R/W

0x0000_0000

0x02C

SPI command register (SPCOM)

W

0x0000_0000

0x030

SPI transmit register (SPITD)

W

0x0000_0000

0x034

SPI receive register (SPIRD)

R

0xFFFF_FFFF

0x038–0xFFF

Reserved

—

—

—

Offset 0x020

Access: Read/write

0

1

2

3

4

5

6

7

8

11 12

15 16

18

19

20

31

R

— LOOP CI CP DIV16 REV M/S EN

LEN

PM

—

OD

—

W

Reset

All zeros

0

—

Reserved. Should be cleared.

1

LOOP Loop mode. Enables local loopback operation. 

0 Normal operation.
1 Loopback mode. Used to test the SPI controller internal functionality, the transmitter output is internally 

connected to the receiver input. The receiver and transmitter operate normally, except that received data 
is ignored.

The SPI acts normally in loop back mode; therefore, negating SPISEL in slave mode stops transmission, 
negating it in master mode and causing and MME error.