Guia De Informação (MPC8308-RDB)índice analíticoMPC8308 PowerQUICC II Pro Processor Hardware Specification11 Overview16Figure 1. MPC8308 Block Diagram162 Electrical Characteristics162.1 Overall DC Electrical Characteristics162.1.1 Absolute Maximum Ratings17Table 1. Absolute Maximum Ratings1172.1.2 Power Supply Voltage Specification17Table 2. Recommended Operating Conditions18Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD192.1.3 Output Driver Characteristics19Table 3. Output Drive Capability192.1.4 Power Sequencing19Figure 3. Power-Up Sequencing Example203 Power Characteristics20Table 4. MPC8308 Power Dissipation20Table 5. MPC8308 Typical I/O Power Dissipation214 Clock Input Timing214.1 DC Electrical Characteristics21Table 6. SYS_CLK_IN DC Electrical Characteristics21Table 7. RTC_PIT_CLOCK DC Electrical Characteristics214.2 AC Electrical Characteristics21Table 8. SYS_CLK_IN AC Timing Specifications22Table 9. RTC_PIT_CLOCK AC Timing Specifications225 RESET Initialization225.1 RESET DC Electrical Characteristics22Table 10. RESET Pins DC Electrical Characteristics225.2 RESET AC Electrical Characteristics23Table 11. RESET Initialization Timing Specifications23Table 12. PLL Lock Times236 DDR2 SDRAM246.1 DDR2 SDRAM DC Electrical Characteristics24Table 13. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V24Table 14. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V24Table 15. Current Draw Characteristics for MVREF256.2 DDR2 SDRAM AC Electrical Characteristics256.2.1 DDR2 SDRAM Input AC Timing Specifications25Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface25Table 17. DDR2 SDRAM Input AC Timing Specifications25Figure 4. Timing Diagram for tDISKEW266.2.2 DDR2 SDRAM Output AC Timing Specifications26Table 18. DDR2 SDRAM Output AC Timing Specifications26Figure 5. Timing Diagram for tDDKHMH28Figure 6. DDR2 SDRAM Output Timing Diagram28Figure 7. DDR2 AC Test Load297 DUART297.1 DUART DC Electrical Characteristics29Table 19. DUART DC Electrical Characteristics297.2 DUART AC Electrical Specifications29Table 20. DUART AC Timing Specifications298 Ethernet: Three-Speed Ethernet, MII Management298.1 Enhanced Three-Speed Ethernet Controller (eTSEC) (10/100/1000 Mbps)-MII/RGMII Electrical Characteristics308.1.1 eTSEC DC Electrical Characteristics30Table 21. MII DC Electrical Characteristics30Table 22. RGMII DC Electrical Characteristics318.2 MII and RGMII AC Timing Specifications318.2.1 MII AC Timing Specifications318.2.1.1 MII Transmit AC Timing Specifications31Table 23. MII Transmit AC Timing Specifications31Figure 8. MII Transmit AC Timing Diagram328.2.1.2 MII Receive AC Timing Specifications32Table 24. MII Receive AC Timing Specifications32Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications33Figure 10. AC Test Load338.2.2 RGMII AC Timing Specifications33Table 25. RGMII AC Timing Specifications33Figure 11. RGMII AC Timing and Multiplexing Diagrams348.3 Ethernet Management Interface Electrical Characteristics348.3.1 MII Management DC Electrical Characteristics35Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V358.3.2 MII Management AC Electrical Specifications35Table 27. MII Management AC Timing Specifications35Figure 12. MII Management Interface Timing Diagram368.4 IEEE Std 1588™ Timer Specifications368.4.1 IEEE 1588 Timer DC Specifications36Table 28. GPIO DC Electrical Characteristics368.4.2 IEEE 1588 Timer AC Specifications37Table 29. IEEE 1588 Timer AC Specifications379 USB379.1 USB Dual-Role Controllers379.1.1 USB DC Electrical Characteristics37Table 30. USB DC Electrical Characteristics379.1.2 USB AC Electrical Specifications38Table 31. USB General Timing Parameters38Figure 13. USB AC Test Load38Figure 14. USB Signals3810 High-Speed Serial Interfaces (HSSI)3910.1 Signal Terms Definition39Figure 15. Differential Voltage Definitions for Transmitter or Receiver4010.2 SerDes Reference Clocks4010.2.1 SerDes Reference Clock Receiver Characteristics41Figure 16. Receiver of SerDes Reference Clocks4110.2.2 DC Level Requirement for SerDes Reference Clocks42Figure 17. Differential Reference Clock Input DC Requirements (External DC-Coupled)43Figure 18. Differential Reference Clock Input DC Requirements (External AC-Coupled)43Figure 19. Single-Ended Reference Clock Input DC Requirements4310.2.3 Interfacing with Other Differential Signaling Levels43Figure 20. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)44Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)45Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)45Figure 23. Single-Ended Connection (Reference Only)4610.2.4 AC Requirements for SerDes Reference Clocks46Table 32. SerDes Reference Clock AC Parameters46Figure 24. Differential Measurement Points for Rise and Fall Time47Figure 25. Single-Ended Measurement Points for Rise and Fall Time Matching4710.2.4.1 Spread Spectrum Clock4810.3 SerDes Transmitter and Receiver Reference Circuits48Figure 26. SerDes Transmitter and Receiver Reference Circuits4811 PCI Express4811.1 DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK4811.2 AC Requirements for PCI Express SerDes Clocks48Table 33. SD_REF_CLK and SD_REF_CLK AC Requirements4811.3 Clocking Dependencies4911.4 Physical Layer Specifications4911.4.1 Differential Transmitter (TX) Output49Table 34. Differential Transmitter (TX) Output Specifications4911.4.2 Transmitter Compliance Eye Diagrams51Figure 27. Minimum Transmitter Timing and Voltage Output Compliance Specifications5211.4.3 Differential Receiver (RX) Input Specifications52Table 35. Differential Receiver (RX) Input Specifications5211.5 Receiver Compliance Eye Diagrams54Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification5511.5.1 Compliance Test and Measurement Load55Figure 29. Compliance Test/Measurement Load5512 Enhanced Local Bus5512.1 Enhanced Local Bus DC Electrical Characteristics56Table 36. Local Bus DC Electrical Characteristics at 3.3 V5612.2 Enhanced Local Bus AC Electrical Specifications56Table 37. Local Bus General Timing Parameters56Figure 30. Local Bus AC Test Load56Figure 31. Local Bus Signals, Non-Special Signals Only57Figure 32. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 257Figure 33. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 45813 Enhanced Secure Digital Host Controller (eSDHC)5813.1 eSDHC DC Electrical Characteristics58Table 38. eSDHC interface DC Electrical Characteristics5813.2 eSDHC AC Timing Specifications (Full Speed Mode)59Table 39. eSDHC AC Timing Specifications for Full Speed Mode59Figure 34. eSDHC Clock Input Timing Diagram6013.2.1 Full Speed Output Path (Write)60Figure 35. Full Speed Output Path6013.2.2 Full Speed Input Path (Read)61Figure 36. Full Speed Input Path6113.3 eSDHC AC Timing Specifications61Table 40. eSDHC AC Timing Specifications for High Speed Mode61Figure 37. eSDHC Clock Input Timing Diagram6213.3.1 High Speed Output Path (Write)63Figure 38. High Speed Output Path6313.3.2 High Speed Input Path (Read)63Figure 39. High Speed Input Path6314 JTAG6414.1 JTAG DC Electrical Characteristics64Table 41. JTAG Interface DC Electrical Characteristics6414.2 JTAG AC Timing Specifications64Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 164Figure 40. AC Test Load for the JTAG Interface65Figure 41. JTAG Clock Input Timing Diagram65Figure 42. TRST Timing Diagram66Figure 43. Boundary-Scan Timing Diagram66Figure 44. Test Access Port Timing Diagram6615 I2C6715.1 I2C DC Electrical Characteristics67Table 43. I2C DC Electrical Characteristics6715.2 I2C AC Electrical Specifications67Table 44. I2C AC Electrical Specifications67Figure 45. I2C AC Test Load68Figure 46. I2C Bus AC Timing Diagram6816 Timers6916.1 Timers DC Electrical Characteristics69Table 45. Timers DC Electrical Characteristics6916.2 Timers AC Timing Specifications69Table 46. Timers Input AC Timing Specifications69Figure 47. Timers AC Test Load6917 GPIO7017.1 GPIO DC Electrical Characteristics70Table 47. GPIO DC Electrical Characteristic7017.2 GPIO AC Timing Specifications70Table 48. GPIO Input AC Timing Specifications70Figure 48. GPIO AC Test Load7018 IPIC7118.1 IPIC DC Electrical Characteristics71Table 49. IPIC DC Electrical Characteristics7118.2 IPIC AC Timing Specifications71Table 50. IPIC Input AC Timing Specifications7119 SPI7119.1 SPI DC Electrical Characteristics71Table 51. SPI DC Electrical Characteristics7119.2 SPI AC Timing Specifications72Table 52. SPI AC Timing Specifications 172Figure 49. SPI AC Test Load72Figure 50. SPI AC Timing in Slave Mode (External Clock) Diagram73Figure 51. SPI AC Timing in Master Mode (Internal Clock) Diagram7320 Package and Pin Listings7320.1 Package Parameters for the MPC8308 MAPBGA7320.2 Mechanical Dimensions of the MPC8308 MAPBGA74Figure 52. Mechanical Dimension and Bottom Surface Nomenclature of the MPC8308 MAPBG7420.3 Pinout Listings75Table 53. MPC8308 Pinout Listing7521 Clocking85Figure 53. MPC8308 Clock Subsystem8521.1 System Clock Domains86Table 54. Configurable Clock Units86Table 55. Operating Frequencies for MPC83088721.2 System PLL Configuration87Table 56. System PLL Ratio87Table 57. CSB Frequency Options8721.3 Core PLL Configuration88Table 58. e300 Core PLL Configuration8822 Thermal8822.1 Thermal Characteristics89Table 59. Package Thermal Characteristics for MAPBGA8922.2 Thermal Management Information8922.2.1 Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance8922.2.2 Estimation of Junction Temperature with Junction-to-Board Thermal Resistance9022.2.3 Experimental Determination of Junction Temperature9023 System Design Information9123.1 System Clocking9123.2 PLL Power Supply Filtering91Figure 54. PLL Power Supply Filter Circuit9123.3 Decoupling Recommendations9223.4 Connection Recommendations9223.5 Output Buffer DC Impedance92Figure 55. Driver Impedance Measurement93Table 60. Impedance Characteristics9323.6 Configuration Pin Muxing9323.7 Pull-Up Resistor Requirements9424 Ordering Information9424.1 Part Numbers Fully Addressed by This Document94Table 61. Part Numbering Nomenclature9424.2 Part Marking95Figure 56. Freescale Part Marking for PBGA Devices95Table 62. SVR Settings9525 Document Revision History96Table 63. Document Revision History96Tamanho: 1 MBPáginas: 97Language: EnglishAbrir o manual
Manual Do Utilizador (MPC8308-RDB)índice analíticoMPC8308 PowerQUICC II Pro Processor Reference Manual1Contents3Figures19Tables37About This Book57Audience57Organization57Suggested Reading59Conventions60Signal Conventions61Acronyms and Abbreviations61Chapter 1 Overview651.1 MPC8308 Overview651.2 MPC8308 Architecture Overview711.2.1 e300 Core711.2.2 DDR2 Memory Controller741.2.3 Dual Enhanced Three-Speed Ethernet Controllers741.2.4 SerDes PHY751.2.5 PCI Express Interface751.2.6 Universal Serial Bus (USB) 2.0751.2.7 Enhanced Local Bus Controller (eLBC)761.2.8 Integrated Programmable Interrupt Controller (IPIC)781.2.9 I2C Interface791.2.10 General Purpose DMA Controller791.2.11 Dual Universal Asynchronous Receiver/Transmitter (DUART)801.2.12 Enhanced Secure Digital Host Controller (eSDHC)801.2.13 System Timers81Chapter 2 Signal Descriptions832.1 Signals Overview832.2 Output Signal States During Reset95Chapter 3 Memory Map993.1 Internal Memory-Mapped Registers993.2 Accessing IMMR Memory from the Local Processor993.3 IMMR Address Map99Chapter 4 Reset, Clocking, and Initialization1034.1 External Signals1034.1.1 Reset Signals1034.1.2 Clock Signals1044.2 Functional Description1054.2.1 Reset Operations1054.2.2 Power-On Reset Flow1074.2.3 Hard Reset Flow1084.3 Reset Configuration1094.3.1 Reset Configuration Signals1094.3.2 Reset Configuration Words1114.3.3 Loading the Reset Configuration Words1184.4 Clocking1244.4.1 System Clock Domains1254.4.2 USB Clocking1264.4.3 Ethernet Clocking1274.5 Memory Map/Register Definitions1274.5.1 Reset Configuration Register Descriptions1274.5.2 Clock Configuration Registers131Chapter 5 System Configuration1375.1 Local Memory Map Overview and Example1375.1.1 Address Translation and Mapping1395.1.2 Window into Configuration Space1395.1.3 Local Access Windows1405.1.4 Local Access Register Descriptions1415.1.5 Precedence of Local Access Windows1495.1.6 Configuring Local Access Windows1495.1.7 Distinguishing Local Access Windows from Other Mapping Functions1495.1.8 Outbound Address Translation and Mapping Windows1505.1.9 Inbound Address Translation and Mapping Windows1505.1.10 Internal Memory Map1505.1.11 Accessing Internal Memory from External Masters1515.2 System Configuration1515.2.1 System Configuration Register Memory Map1515.2.2 System Configuration Registers1525.3 Software Watchdog Timer (WDT)1685.3.1 WDT Overview1685.3.2 WDT Features1695.3.3 WDT Modes of Operation1695.3.4 WDT Memory Map/Register Definition1705.3.5 Functional Description1735.3.6 Initialization/Application Information (WDT Programming Guidelines)1755.4 Real Time Clock (RTC) Module1755.4.1 Overview1755.4.2 Features1765.4.3 Assumptions1765.4.4 Modes of operation1765.4.5 External Signal Description1775.4.6 RTC Memory Map/Register Definition1775.4.7 Functional Description1815.4.8 RTC Reset Sequence1835.4.9 RTC Initialization Sequence1835.5 Periodic Interval Timer (PIT)1835.5.1 PIT Overview1835.5.2 PIT Features1845.5.3 PIT Modes of Operation1845.5.4 PIT External Signal Description1845.5.5 PIT Memory Map/Register Definition1855.5.6 Functional Description1885.5.7 PIT Programming Guidelines1895.6 General-Purpose Timers (GTMs)1895.6.1 GTM Overview1895.6.2 GTM Features1905.6.3 GTM Modes of Operation1915.6.4 GTM External Signal Description1925.6.5 GTM Memory Map/Register Definition1935.6.6 Functional Description2025.6.7 Initialization/Application Information (Programming Guidelines for GTM Registers)2055.7 Power Management Control (PMC)2055.7.1 External Signal Description2065.7.2 PMC Memory Map/Register Definition2065.7.3 Functional Description207Chapter 6 Arbiter and Bus Monitor2116.1 Overview2116.1.1 Coherent System Bus Overview2116.2 Arbiter Memory Map/Register Definition2126.2.1 Arbiter Configuration Register (ACR)2136.2.2 Arbiter Timers Register (ATR)2146.2.3 Arbiter Event Enable Register (AEER)2156.2.4 Arbiter Event Register (AER)2166.2.5 Arbiter Interrupt Definition Register (AIDR)2176.2.6 Arbiter Mask Register (AMR)2186.2.7 Arbiter Event Attributes Register (AEATR)2196.2.8 Arbiter Event Address Register (AEADR)2206.2.9 Arbiter Event Response Register (AERR)2216.3 Functional Description2226.3.1 Arbitration Policy2226.3.2 Bus Error Detection2256.4 Initialization/Applications Information2286.4.1 Initialization Sequence2286.4.2 Error Handling Sequence228Chapter 7 e300 Processor Core Overview2297.1 Overview2297.1.1 Features2317.1.2 Instruction Unit2347.1.3 Independent Execution Units2357.1.4 Completion Unit2367.1.5 Memory Subsystem Support2367.1.6 Bus Interface Unit (BIU)2387.1.7 System Support Functions2397.2 e300 Processor and System Version Numbers2417.3 PowerPC Architecture Implementation2417.4 Implementation-Specific Information2427.4.1 Register Model2427.4.2 Instruction Set and Addressing Modes2547.4.3 Cache Implementation2577.4.4 Interrupt Model2597.4.5 Memory Management2637.4.6 Instruction Timing2647.4.7 Core Interface2657.4.8 Debug Features2677.5 Differences Between Cores268Chapter 8 Integrated Programmable Interrupt Controller (IPIC)2718.1 Introduction2718.2 Features2748.3 Modes of Operation2748.3.1 Core Enable Mode2748.3.2 Core Disable Mode2748.4 External Signal Description2758.4.1 Overview2758.4.2 Detailed Signal Descriptions2758.5 Memory Map/Register Definition2768.5.1 System Global Interrupt Configuration Register (SICFR)2788.5.2 System Global Interrupt Vector Register (SIVCR)2798.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L)2828.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A)2848.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B)2858.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C)2868.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D)2868.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L)2878.5.9 System Internal Interrupt Control Register (SICNR)2888.5.10 System External Interrupt Pending Register (SEPNR)2908.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)2918.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)2928.5.13 System External Interrupt Mask Register (SEMSR)2928.5.14 System External Interrupt Control Register (SECNR)2938.5.15 System Error Status Register (SERSR)2958.5.16 System Error Mask Register (SERMR)2958.5.17 System Error Control Register (SERCR)2968.5.18 System External interrupt Polarity Control Register (SEPCR)2968.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L)2978.5.20 System External Interrupt Force Register (SEFCR)2998.5.21 System Error Force Register (SERFR)2998.5.22 System Critical Interrupt Vector Register (SCVCR)3008.5.23 System Management Interrupt Vector Register (SMVCR)3008.6 Functional Description3018.6.1 Interrupt Types3018.6.2 Interrupt Configuration3028.6.3 Internal Interrupts Group Relative Priority3038.6.4 Mixed Interrupts Group Relative Priority3038.6.5 Highest Priority Interrupt3048.6.6 Interrupt Source Priorities3048.6.7 Masking Interrupt Sources3088.6.8 Interrupt Vector Generation and Calculation3098.6.9 Machine Check Interrupts3098.7 Message Shared Interrupts3108.7.1 Memory Map/Register Definition3108.7.2 Message Shared Registers310Chapter 9 DDR Memory Controller3159.1 Introduction3159.2 Features3169.2.1 Modes of Operation3179.3 External Signal Descriptions3179.3.1 Signals Overview3179.3.2 Detailed Signal Descriptions3209.4 Memory Map/Register Definition3239.4.1 Register Descriptions3249.5 Functional Description3529.5.1 DDR SDRAM Interface Operation3569.5.2 DDR SDRAM Address Multiplexing3579.5.3 JEDEC Standard DDR SDRAM Interface Commands3599.5.4 DDR SDRAM Interface Timing3619.5.5 DDR SDRAM Mode-Set Command Timing3659.5.6 DDR SDRAM Registered DIMM Mode3659.5.7 DDR SDRAM Write Timing Adjustments3669.5.8 DDR SDRAM Refresh3679.5.9 DDR Data Beat Ordering3709.5.10 Page Mode and Logical Bank Retention3719.5.11 Error Checking and Correcting (ECC)3729.5.12 Error Management3749.6 Initialization/Application Information3749.6.1 DDR SDRAM Initialization Sequence376Chapter 10 Enhanced Local Bus Controller37710.1 Introduction37710.1.1 Overview37810.1.2 Features37810.1.3 Modes of Operation37910.2 External Signal Descriptions38010.3 Memory Map/Register Definition38310.3.1 Register Descriptions38510.4 Functional Description41510.4.1 Basic Architecture41610.4.2 General-Purpose Chip-Select Machine (GPCM)41810.4.3 Flash Control Machine (FCM)42910.4.4 User-Programmable Machines (UPMs)44410.5 Initialization/Application Information46010.5.1 Interfacing to Peripherals in Different Address Modes46010.5.2 Interface to Different Port-Size Devices46110.5.3 Command Sequence Examples for NAND Flash EEPROM46210.5.4 Interfacing to Fast-Page Mode DRAM Using UPM46610.5.5 Interfacing to ZBT SRAM Using UPM476Chapter 11 Enhanced Secure Digital Host Controller47911.1 Overview47911.2 Features48111.2.1 Data Transfer Modes48211.3 External Signal Description48211.4 Memory Map/Register Definition48311.4.1 DMA System Address Register (DSADDR)48511.4.2 Block Attributes Register (BLKATTR)48511.4.3 Command Argument Register (CMDARG)48611.4.4 Transfer Type Register (XFERTYP)48711.4.5 Command Response 0-3 (CMDRSP0-3)49011.4.6 Buffer Data Port Register (DATPORT)49211.4.7 Present State Register (PRSSTAT)49311.4.8 Protocol Control Register (PROCTL)49711.4.9 System Control Register (SYSCTL)50011.4.10 Interrupt Status Register (IRQSTAT)50211.4.11 Interrupt Status Enable Register (IRQSTATEN)50611.4.12 Interrupt Signal Enable Register (IRQSIGEN)50911.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)51111.4.14 Host Controller Capabilities (HOSTCAPBLT)51311.4.15 Watermark Level Register (WML)51411.4.16 Force Event Register (FEVT)51411.4.17 Host Controller Version Register (HOSTVER)51611.4.18 DMA Control Register (DCR)51611.5 Functional Description51611.5.1 Data Buffer51711.5.2 DMA CSB Interface51911.5.3 SD Protocol Unit52011.5.4 Clock & Reset Manager52211.5.5 Clock Generator52211.5.6 SDIO Card Interrupt52211.5.7 Card Insertion and Removal Detection52411.5.8 Power Management52411.6 Initialization/Application Information52511.6.1 Command Send and Response Receive Basic Operation52511.6.2 Card Identification Mode52611.6.3 Card Access53011.6.4 Switch Function53511.6.5 Commands for MMC/SD/SDIO53811.7 Software Restrictions54311.7.1 Initialization Active54311.7.2 Software Polling Procedure54311.7.3 Suspend Operation54311.7.4 Data Port Access54311.7.5 Multi-block Read543Chapter 12 DMA Controller (DMAC)54512.1 Overview54512.1.1 Features54612.2 DMAC Memory Map/Register Definition54612.2.1 DMA Control Register (DMACR)54712.3 DMA Error Status (DMAES)55012.3.1 DMA Enable Error Interrupt Register (DMAEEI)55212.3.2 DMA Set Enable Error Interrupt (DMASEEI)55312.3.3 DMA Clear Enable Error Interrupt (DMACEEI)55312.3.4 DMA Clear Interrupt Request (DMACINT)55412.3.5 DMA Clear Error (DMACERR)55512.3.6 DMA Set START Bit (DMASSRT)55512.3.7 DMA Clear DONE Status (DMACDNE)55612.3.8 DMA Interrupt Request Register (DMAINT)55612.3.9 DMA Error Register (DMAERR)55712.3.10 DMA General Purpose Output Register (DMAGPOR)55812.3.11 DMA Channel n Priority (DCHPRIn), n = 0-1555912.3.12 Transfer Control Descriptor (TCD)56012.4 Functional Description56812.4.1 DMA Microarchitecture56812.4.2 DMA Basic Data Flow56912.5 Initialization/Application Information57212.5.1 DMA Initialization57212.5.2 DMA Programming Errors57312.6 DMA Transfer57312.6.1 Single Request57312.6.2 Multiple Requests57412.7 TCD Status57612.7.1 Minor Loop Complete57612.7.2 Active Channel TCD Reads57612.7.3 Preemption status57612.8 Channel Linking57712.9 Programming during channel execution57712.9.1 Dynamic priority changing57712.9.2 Dynamic channel linking and dynamic scatter/gather578Chapter 13 Universal Serial Bus Interface57913.1 Introduction57913.1.1 Overview58013.1.2 Features58013.1.3 Modes of Operation58013.2 External Signals58113.2.1 ULPI Interface58113.3 Memory Map/Register Definitions58213.3.1 Capability Registers58413.3.2 Operational Registers58813.4 Functional Description62213.4.1 System Interface62213.4.2 DMA Engine62313.4.3 FIFO RAM Controller62313.4.4 PHY Interface62313.5 Host Data Structures62313.5.1 Periodic Frame List62413.5.2 Asynchronous List Queue Head Pointer62513.5.3 Isochronous (High-Speed) Transfer Descriptor (iTD)62613.5.4 Split Transaction Isochronous Transfer Descriptor (siTD)63013.5.5 Queue Element Transfer Descriptor (qTD)63413.5.6 Queue Head64013.5.7 Periodic Frame Span Traversal Node (FSTN)64413.6 Host Operations64613.6.1 Host Controller Initialization64613.6.2 Power Port64713.6.3 Reporting Over-Current64713.6.4 Suspend/Resume64713.6.5 Schedule Traversal Rules65013.6.6 Periodic Schedule Frame Boundaries vs. Bus Frame Boundaries65113.6.7 Periodic Schedule65313.6.8 Managing Isochronous Transfers Using iTDs65413.6.9 Asynchronous Schedule65913.6.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads66313.6.11 Ping Control66713.6.12 Split Transactions66813.6.13 Port Test Modes69613.6.14 Interrupts69713.7 Device Data Structures70113.7.1 Endpoint Queue Head70213.7.2 Endpoint Transfer Descriptor (dTD)70513.8 Device Operational Model70713.8.1 Device Controller Initialization70713.8.2 Port State and Control70813.8.3 Managing Endpoints71113.8.4 Managing Queue Heads72113.8.5 Managing Transfers with Transfer Descriptors72313.8.6 Servicing Interrupts72613.9 Deviations from the EHCI Specifications72713.9.1 Embedded Transaction Translator Function72813.9.2 Device Operation73113.9.3 Non-Zero Fields the Register File73213.9.4 SOF Interrupt73213.9.5 Embedded Design73213.9.6 Miscellaneous Variations from EHCI73213.10 Timing Diagrams734Chapter 14 PCI Express Interface Controller73914.1 Introduction73914.1.1 MPC8308 as a PCI Express Initiator74114.1.2 MPC8308 as a PCI Express Target74114.1.3 Features74214.1.4 Modes of Operation74214.2 External Signal Descriptions74314.3 Memory Map/Register Definitions74314.3.1 PCI Express Memory Map74314.4 PCI Express Core Configuration Header Registers75214.4.1 Common PCI Express-Compatible Configuration Header Registers75214.4.2 Type 0 PCI Express-Compatible Configuration Header Registers75914.4.3 Type 1 PCI-Compatible Configuration Header Registers76514.4.4 PCI Express-Compatible Device-Specific Configuration Space Registers77414.4.5 PCI Express Extended Configuration Space79014.4.6 PCI Express Controller Internal Control and Status Registers (CSRs)80014.4.7 PCI Express BAR Configuration Registers (EP Mode)81014.4.8 PCI Express Extended Status and Control Registers81214.5 PCI Express CSB Bridge81414.5.1 PCI Express CSB Bridge Configuration Space81514.5.2 Global Registers81514.5.3 PCI Express Outbound PIO Registers81814.5.4 PCI Express Inbound PIO Registers82014.5.5 DMA Registers82114.5.6 Mailbox Registers82614.5.7 PCI Express Host Interrupt Registers82814.5.8 CSB System Interrupt Registers83214.5.9 PCI Express Power Management Registers84114.5.10 PCI Express Outbound Address Mapping Registers84214.5.11 PCI Express EP Inbound Address Translation Registers84514.5.12 PCI Express RC Inbound Address Mapping Registers84614.6 Functional Description84914.6.1 Architecture85014.6.2 Interrupts86014.6.3 Mailbox86214.6.4 Power Management86414.6.5 Hot Reset86514.7 Initialization/Application Information86514.7.1 Initialization Sequence86514.8 DMA Functional Operation86614.8.1 DMA Descriptor Format86614.8.2 Write DMA86814.8.3 Read DMA86914.8.4 Descriptor-Based DMA870Chapter 15 SerDes PHY87315.1 Introduction87315.1.1 Overview87315.1.2 Features87315.1.3 Mode of Operation87415.1.4 Clock87415.2 External Signals87415.3 Memory Map/Registers87515.3.1 SerDes Control Register 0 (SRDSCR0)87615.3.2 SerDes Control Register 1 (SRDSCR1)87815.3.3 SerDes Control Register 2 (SRDSCR2)87915.3.4 SerDes Control Register 3 (SRDSCR3)88015.3.5 SerDes Control Register 4 (SRDSCR4)88115.3.6 SerDesn Reset Control Register (SRDSRSTCTL)88215.4 Initialization Sequence and Reset88215.5 Power Management: Power Down883Chapter 16 Enhanced Three-Speed Ethernet Controllers88516.1 Overview88516.2 Features88616.3 Modes of Operation88816.4 External Signals Description88916.4.1 Detailed Signal Descriptions89116.5 Memory Map/Register Definition89316.5.1 Top-Level Module Memory Map89416.5.2 Detailed Memory Map89416.5.3 Memory-Mapped Register Descriptions90516.6 Functional Description100416.6.1 Connecting to Physical Interfaces on Ethernet100516.6.2 Gigabit Ethernet Controller Channel Operation100816.6.3 TCP/IP Off-Load102316.6.4 Quality of Service (QoS) Provision102816.6.5 Lossless Flow Control103816.6.6 Hardware Assist for IEEE Std. 1588 Compliant Timestamping104116.6.7 Buffer Descriptors104816.7 Initialization/Application Information105516.7.1 Interface Mode Configuration105616.7.2 MAC: Half-Duplex Collision on FCS of Short Frame1062Chapter 17 I2C Interface106317.1 Introduction106317.1.1 Features106417.1.2 Modes of Operation106417.2 External Signal Descriptions106517.2.1 Signal Overview106517.2.2 Detailed Signal Descriptions106517.3 Memory Map/Register Definition106617.3.1 Register Descriptions106717.4 Functional Description107217.4.1 Transaction Protocol107217.4.2 Arbitration Procedure107617.4.3 Handshaking107717.4.4 Clock Control107717.4.5 Boot Sequencer Mode107817.5 Initialization/Application Information108317.5.1 Interrupt Service Routine Flowchart108317.5.2 Initialization Sequence108517.5.3 Generation of START108517.5.4 Post-Transfer Software Response108517.5.5 Generation of STOP108617.5.6 Generation of Repeated START108617.5.7 Generation of SCL When SDA is Negated108617.5.8 Slave Mode Interrupt Service Routine1086Chapter 18 DUART108918.1 Overview108918.1.1 Features109018.1.2 Modes of Operation109018.2 External Signal Descriptions109118.2.1 Signal Overview109118.2.2 Detailed Signal Descriptions109118.3 Memory Map/Register Definition109118.3.1 Register Descriptions109318.4 Functional Description110418.4.1 Serial Interface110518.4.2 Baud-Rate Generator Logic110618.4.3 Local Loopback Mode110718.4.4 Errors110718.4.5 FIFO Mode110718.5 DUART Initialization/Application Information1109Chapter 19 Serial Peripheral Interface111119.1 Overview111119.1.1 Features111219.1.2 SPI Transmission and Reception Process111219.1.3 Modes of Operation111319.2 External Signal Descriptions111619.2.1 Overview111619.2.2 Detailed Signal Descriptions111619.3 Memory Map/Register Definition111719.3.1 Register Descriptions111819.4 Initialization/Application Information112519.4.1 SPI Master Programming Example112519.4.2 SPI Slave Programming Example1125Chapter 20 JTAG/Testing Support112720.1 Overview112720.2 JTAG Signals112720.2.1 External Signal Descriptions112820.3 JTAG Registers and Scan Chains1129Chapter 21 General Purpose I/O (GPIO)113121.1 Introduction113121.1.1 Overview113121.1.2 Features113121.2 External Signal Description113221.2.1 Signals Overview113221.3 Memory Map/Register Definition113221.3.1 GPIO Direction Register (GPDIR)113321.3.2 GPIO Open Drain Register (GPODR)113321.3.3 GPIO Data Register (GPDAT)113421.3.4 GPIO Interrupt Event Register (GPIER)113421.3.5 GPIO Interrupt Mask Register (GPIMR)113421.3.6 GPIO Interrupt Control Register (GPICR)1135Appendix A Complete List of Configuration, Control, and Status Registers1137A.1 Local Access Windows1137A.2 System Configuration Registers1138A.3 Watchdog Timer (WDT)1139A.4 Real Time Clock (RTC)1139A.5 Periodic Interval Timer (PIT)1139A.6 General Purpose (Global) Timers (GTMs)1140A.7 Integrated Programmable Interrupt Controller (IPIC)1141A.8 System Arbiter1142A.9 Reset Configuration1142A.10 Clock Configuration1143A.11 Power Management Controller (PMC)1143A.12 General Purpose I/O (GPIO)1144A.13 DDR Memory Controller1144A.14 I2C Controller1145A.15 DUART1146A.16 Enhanced Local Bus Controller (eLBC)1147A.17 Serial Peripheral Interface (SPI)1148A.18 DMA Controller1149A.19 PCI Express Controller1150A.20 Enhanced Three-Speed Ethernet Controllers (eTSECs)1157A.21 SerDes PHY1167A.22 Enhanced Secure Digital Host Controller (eSDHC)1168A.23 Universal Serial Bus (USB) Interface1168Appendix B Revision History1171Tamanho: 5 MBPáginas: 1176Language: EnglishAbrir o manual