Freescale Semiconductor Reference Design System for MPC8308 MPC8308-RDB MPC8308-RDB Manual Do Utilizador

Freescale Semiconductor

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such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash 
EPROM, Flash EPROM, burstable RAM, and other peripherals.

The eLBC also includes a number of data checking and protection features such as data parity generation 
and checking, write protection, and a bus monitor to ensure that each bus cycle is terminated within a 
user-specified period.

The eLBC provides two Write Enable signals to allow single-byte write access to external 16-bit eLBC 
slave devices.

The main features of the enhanced local bus controller (eLBC) are as follows:

•

Memory controller with four memory banks (chip selects)

— 32-bit address decoding with mask

— Variable memory block sizes (32 Kbytes to 2 Gbytes in FCM mode, 32 Kbytes to 64 Mbytes 

in UPM mode, and 32 Kbytes to 64 Mbytes in GPCM mode)

— Selection of control signal generation on a per-bank basis

— Data buffer controls activated on a per-bank basis

— Up to 256-byte bursts, arbitrarily aligned

— Automatic segmentation of large transactions into memory accesses optimized for bus width 

and addressing capability

— Write-protection capability

— Atomic operation

•

General-purpose chip-select machine (GPCM)

— Compatible with SRAM, EPROM, NOR Flash EEPROM, FEPROM, and peripherals

— Global (boot) chip-select available at system reset

— Boot chip-select support for 8- and 16-bit devices

— Minimum three-clock access to external devices

— Two byte-write-enable signals (LWE[0:1])

— Output enable signal (LOE)

— External access termination signal (LGTA)

•

NAND Flash control machine (FCM)

— Compatible with small (512 + 16 bytes) and large (2048 + 64 bytes) page parallel NAND 

Flash EEPROM

— Global (boot) chip-select available at system reset, with 4-Kbyte boot block buffer for 

execute-in-place boot loading

— Boot chip-select support for 8-bit devices

— Dual 2-Kbyte/eight 512-byte buffers allow simultaneous data transfer during Flash reads and 

programming

— Interrupt-driven block transfer for reads and writes

— Programmable command and data transfer sequences of up to eight steps supported

— Generic command and address registers support proprietary Flash interfaces