Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador
Códigos do produto
MSC8156EVM
MSC8156 Reference Manual, Rev. 2
25-24
Freescale
Semiconductor
Debugging, Profiling, and Performance Monitoring
25.2.4 SC3850 Debug and Profiling
The MSC8156 device contains six extended DSP cores. Each DSP core subsystem supports the
debug and profiling capabilities. When the DSP core subsystem is in the Debug state, the SC3850
core enters its Debug processing state, and instruction processing is halted. After a delay, all
subsequent DSP core subsystem activity ceases (as reflected in the BUSY bit in the JTAG
accessible OCE register RD_STATUS). In this state, a debugging agent external to the DSP core
subsystem can access various internal DSP core subsystem registers and memory locations to
develop and debug applications. The DSP core subsystem enters Debug state after one of the
following occurs:
debug and profiling capabilities. When the DSP core subsystem is in the Debug state, the SC3850
core enters its Debug processing state, and instruction processing is halted. After a delay, all
subsequent DSP core subsystem activity ceases (as reflected in the BUSY bit in the JTAG
accessible OCE register RD_STATUS). In this state, a debugging agent external to the DSP core
subsystem can access various internal DSP core subsystem registers and memory locations to
develop and debug applications. The DSP core subsystem enters Debug state after one of the
following occurs:
Assertion of dedicated input signals (normally connected to the debugging agent).
Execution of the DEBUG or DEBUGEV instruction by the core.
An event is detected by the DPU (depending on the configuration of the DPU and OCE).
An initiator or peripheral device writes a certain value to GCR2 control register.
Execution of the DEBUG or DEBUGEV instruction by the core.
An event is detected by the DPU (depending on the configuration of the DPU and OCE).
An initiator or peripheral device writes a certain value to GCR2 control register.
Note:
See the MSC8156 SC3850 DSP Core Subsystem Reference Manual for details.
The DSP core subsystem exits the Debug state when it receives the proper transaction from the
external debugging agent through the JTAG port or a reset signal is asserted.
external debugging agent through the JTAG port or a reset signal is asserted.
25.2.5 L1 ICache and DCache Debug and Profiling
The L1 ICache and DCache L2 Cache/M2 blocks in each DSP core subsystem have
block-specific Debug modes that are ctivated only when the DSP core subsystem is in the Debug
state and certain values are written to their respective control registers. In this mode, the internal
state of the caches (tags, valid bits, PLRU table and cache array) can be read with JTAG-inserted
core commands.
block-specific Debug modes that are ctivated only when the DSP core subsystem is in the Debug
state and certain values are written to their respective control registers. In this mode, the internal
state of the caches (tags, valid bits, PLRU table and cache array) can be read with JTAG-inserted
core commands.
Note:
See the MSC8156 MSC3850 Core Subsystem Reference Manual for details.
25.2.6 DMA Controller Debug and Profiling
The DMA controller can enter debug mode only as the result of an external debug request. When
this occurs, the channel logic masks all channel requests generated towards the bus interface and
finishes all pipelined requests in the bus interface and M bus. In this state, a debugging agent
external to the MSC8156 can access the DMA controller PRAM through JTAG bus.
this occurs, the channel logic masks all channel requests generated towards the bus interface and
finishes all pipelined requests in the bus interface and M bus. In this state, a debugging agent
external to the MSC8156 can access the DMA controller PRAM through JTAG bus.
25.2.6.1 Debug Errors
The DMA support debugging errors and indications, such as:
BD_SIZE, MD_BD_SIZE programmed with a value of zero
Channel information that causes an illegal addresses on bus interface ports A/B.
Early Dead Line serve First Violation.
Channel information that causes an illegal addresses on bus interface ports A/B.
Early Dead Line serve First Violation.