Manual Do Utilizador (MSC8156EVM)índice analíticoMSC8156EVM Kernels Starting Guide11 Introduction12 What You Need to Run this Project23 Test Procedures34 Common Kernel Example Demonstration44.1 FIR_complex_16x1654.2 Complex Radix-4 FFT/IFFT 16x1664.3 Complex Radix-2 and Radix-4 FFT/IFFT 16x1694.4 IIR104.5 Division 16¥16124.6 Ln134.7 Matrix Inversion Complex 2¥2144.8 Matrix Inversion Complex 4¥415Tamanho: 200 KBPáginas: 16Language: EnglishAbrir o manual
Guia De Informação (MSC8156EVM)índice analíticoMSC8156 Product Brief11 Features21.1 Block Diagram21.2 Critical Performance Metrics41.3 Device Level Features41.4 Module Level Features52 Developer Environment142.1 Tools142.2 Application Software15Tamanho: 500 KBPáginas: 18Language: EnglishAbrir o manual
Ficha De Dados (MSC8156EVM)índice analíticoMSC8156 Six-Core Digital Signal Processor11 Pin Assignment41.1 FC-PBGA Ball Layout Diagram41.2 Signal List By Ball Location52 Electrical Characteristics242.1 Maximum Ratings242.2 Recommended Operating Conditions252.3 Thermal Characteristics252.4 CLKIN Requirements262.5 DC Electrical Characteristics262.5.1 DDR SDRAM DC Electrical Characteristics262.5.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics272.5.1.2 DDR3 (1.5V) SDRAM DC Electrical Characteristics272.5.1.3 DDR2/DDR3 SDRAM Capacitance282.5.1.4 DDR Reference Current Draw282.5.2 High-Speed Serial Interface (HSSI) DC Electrical Characteristics282.5.2.1 Signal Term Definitions282.5.2.2 SerDes Reference Clock Receiver Characteristics302.5.2.3 SerDes Transmitter and Receiver Reference Circuits312.5.3 DC-Level Requirements for SerDes Interfaces312.5.3.1 DC-Level Requirements for SerDes Reference Clocks312.5.3.2 DC-Level Requirements for PCI Express Configurations332.5.3.3 DC-Level Requirements for Serial RapidIO Configurations342.5.3.4 DC-Level Requirements for SGMII Configurations342.5.4 RGMII and Other Interface DC Electrical Characteristics362.6 AC Timing Characteristics372.6.1 DDR SDRAM AC Timing Specifications372.6.1.1 DDR SDRAM Input AC Timing Specifications372.6.1.2 DDR SDRAM Output AC Timing Specifications382.6.1.3 DDR2 and DDR3 SDRAM Differential Timing Specifications402.6.2 HSSI AC Timing Specifications412.6.2.1 AC Requirements for SerDes Reference Clock412.6.2.2 PCI Express AC Physical Layer Specifications432.6.2.3 Serial RapidIO AC Timing Specifications442.6.2.4 SGMII AC Timing Specifications452.6.3 TDM Timing472.6.4 Timers AC Timing Specifications482.6.5 Ethernet Timing492.6.5.1 Management Interface Timing492.6.5.2 RGMII AC Timing Specifications502.6.6 SPI Timing512.6.7 Asynchronous Signal Timing532.6.8 JTAG Signals533 Hardware Design Considerations553.1 Power Supply Ramp-Up Sequence553.1.1 Clock, Reset, and Supply Coordination553.1.2 Power-On Ramp Time563.1.3 Power Supply Guidelines563.1.4 Reset Guidelines573.2 PLL Power Supply Design Considerations583.3 Clock and Timing Signal Board Layout Considerations593.4 SGMII AC-Coupled Serial Link Connection Example593.5 Connectivity Guidelines603.5.1 DDR Memory Related Pins603.5.1.1 DDR Interface Is Not Used603.5.1.2 DDR Interface Is Used With 32-Bit DDR Memory Only613.5.1.3 ECC Unused Pin Connections623.5.1.4 DDR2 Unused MAPAR Pin Connections623.5.2 HSSI-Related Pins623.5.2.1 HSSI Port Is Not Used623.5.2.2 HSSI Specific Lane Is Not Used633.5.3 RGMII Ethernet Related Pins643.5.4 TDM Interface Related Pins643.5.5 Miscellaneous Pins653.6 Guide to Selecting Connections for Remote Power Supply Sensing654 Ordering Information665 Package Information676 Product Documentation687 Revision History68Tamanho: 1000 KBPáginas: 69Language: EnglishAbrir o manual
Manual Do Utilizador (MSC8156EVM)índice analíticoMSC8156 Reference Manual1Contents5About This Book41Before Using This Manual-Important Note42Audience and Helpful Hints42Notational Conventions and Definitions43Conventions for Registers44Organization44Other MSC8156 Documentation47Further Reading47Document Change History48Overview 1491.1 Features501.2 Block Diagram611.3 Architecture621.4 StarCore SC3850 DSP Subsystem621.4.1 Enhancements631.4.2 StarCore SC3850 DSP Core641.4.3 L1 Instruction Cache651.4.4 L1 Data Cache651.4.5 L2 Unified Cache/M2 Memory661.4.6 Memory Management Unit (MMU)661.4.7 Debug and Profiling Unit (DPU)661.4.8 Extended Programmable Interrupt Controller671.4.9 Timer671.5 MAPLE-B671.6 Chip-Level Arbitration and Switching System (CLASS)681.7 M3 Memory681.8 Clocks691.9 DDR Controllers (DDRC1 and DDRC2)691.10 DMA Controller701.11 High Speed System Interface701.11.1 Serial RapidIO Subsystem711.11.1.1 Serial RapidIO and Host Interactions721.11.1.2 RapidIO Messaging Unit (RMU) Operation731.11.2 PCI Express741.11.3 OCN-DMA Controllers751.11.4 OCN Fabric751.11.5 SRIO Port Controller Modules (SRIOn)751.11.6 SerDes PHY Interfaces751.12 QUICC Engine Subsystem761.12.1 Ethernet Controllers771.12.2 Serial Peripheral Interface (SPI)781.13 TDM781.14 Global Interrupt Controller (GIC)791.15 UART791.16 Timers791.17 Hardware Semaphores791.18 Virtual Interrupts801.19 I2C Interface801.20 GPIOs801.21 Boot Options801.22 JTAG811.23 Developer Environment821.23.1 Tools821.23.2 Application Software831.24 Example Applications831.24.1 Use Case 1: 3G-LTE Basic System831.24.2 Use Case 2: 3G-LTE System841.24.3 Use Case 3: 3G-LTE System841.24.4 Use Case 4: TD-SCDMA System851.24.5 Use Case 5: WiMAX Basic System851.24.6 Use Case 6: WiMAX System861.24.7 Use Case 7: WCDMA Basic System86SC3850 Core Overview 2872.1 Core Architecture Features882.2 StarCore SC3850 Core Architecture90External Signals 3933.1 Power Signals963.2 Clock Signals983.3 Reset and Configuration Signals983.4 Memory Controller 1 and 21023.5 SerDes Multiplexed Signals for the Serial RapidIO, PCI Express, and SGMII Interfaces1033.6 TDM and Ethernet Signals1083.7 Serial Peripheral Interface (SPI) Signal Summary1123.8 GPIO/Maskable Interrupt Signal Summary1123.9 Timer Signals1173.10 UART Signals1183.11 I2C Signals1183.12 External DMA Signals1193.13 Other Interrupt Signals1203.14 OCE Event and JTAG Test Access Port Signals121Chip-Level Arbitration and Switching System (CLASS) 41234.1 CLASS Features1244.2 Functional Description1254.2.1 Expander Module and Transaction Flow1264.2.2 Multiplexer and Arbiter Module1264.2.2.1 CLASS Arbiter1264.2.2.1.1 Weighted Arbitration1274.2.2.1.2 Late Arbitration1274.2.2.1.3 Priority Masking1274.2.2.1.4 Auto Priority Upgrade1274.2.2.2 CLASS Multiplexer1274.2.3 Normalizer Module1284.2.4 CLASS Control Interface (CCI)1284.3 MSC8156 Initiator CLASS Access Priorities1284.4 CLASS Error Interrupts1304.5 CLASS Debug Profiling Unit1314.5.1 Profiling1314.5.2 Watch Point Unit1324.5.3 Event Selection1334.5.4 Debug and Profiling Events1364.6 CLASS Reset1364.6.1 Soft Reset1364.6.2 Hard Reset1364.7 Limitations1364.8 Programming Model1374.8.1 CLASS Priority Mapping Registers (C0PMRx)1384.8.2 CLASS Priority Auto Upgrade Value Registers (C0PAVRx)1404.8.3 CLASS Priority Auto Upgrade Control Registers (C0PACRx)1414.8.4 CLASS Error Address Registers (C0EARx)1424.8.5 CLASS Error Extended Address Registers (C0EEARx)1434.8.6 CLASS Initiator Profiling Configuration Registers (C0IPCRx)1454.8.7 CLASS Initiator Watch Point Control Registers (C0IWPCRx)1474.8.8 CLASS Arbitration Weight Registers (C0AWRx)1484.8.9 CLASS0 Start Address Decoder x (C0SADx)1494.8.10 CLASS End Address Decoder x (C0EADx)1504.8.11 CLASS Attributes Decoder x (C0ATDx)1514.8.12 CLASS IRQ Status Register (C0ISR)1524.8.13 CLASS IRQ Enable Register (C0IER)1534.8.14 CLASS Target Profiling Configuration Register (C0TPCR)1544.8.15 CLASS Profiling Control Register (C0PCR)1554.8.16 CLASS Watch Point Control Registers (C0WPCR)1564.8.17 CLASS Watch Point Access Configuration Register (C0WPACR)1584.8.18 CLASS Watch Point Extended Access Configuration Register (C0WPEACR)1594.8.19 CLASS Watch Point Address Mask Registers (C0WPAMR)1604.8.20 CLASS Profiling Time-Out Registers (C0PTOR)1614.8.21 CLASS Target Watch Point Control Registers (C0TWPCR)1624.8.22 CLASS Profiling IRQ Status Register (C0PISR)1634.8.23 CLASS Profiling IRQ Enable Register (C0PIER)1644.8.24 CLASS Profiling Reference Counter Register (C0PRCR)1644.8.25 CLASS Profiling General Counter Registers (C0PGCRx)1654.8.26 CLASS Arbitration Control Register (C0ACR)166Reset 51675.1 Reset Operations1675.1.1 Reset Sources1685.1.2 Reset Actions1685.1.3 Power-On Reset Flow1695.1.4 Detailed Power-On Reset Flow1705.1.5 HRESET Flow1735.1.6 SRESET Flow1735.2 Reset Configuration1745.2.1 Reset Configuration Signals1745.2.2 Reset Configuration Words Source1745.2.3 Reset Configuration Input Signal Selection and Reset Sequence Duration1755.2.4 Reset Configuration Words1755.2.5 Loading The Reset Configuration Words1755.2.5.1 Loading From an I2C EEPROM (RCW_SRC[0-2] = 001 or 010)1765.2.5.1.1 Using The Boot Sequencer For Reset Configuration1765.2.5.1.2 EEPROM Slave Address1765.2.5.1.3 EEPROM Data Format In Reset Configuration Mode1765.2.5.1.4 Single Device Loading From I2C EEPROM1775.2.5.1.5 Loading Multiple Devices From a Single I2C EEPROM1775.2.5.2 Loading Multiplexed RCW from External Pins (RCW_SRC[0-2] = 000)1795.2.5.3 Loading Reduced RCW From External Pins (RCW_SRC[0-2] = 011)1805.2.5.3.1 Reduced External Reset Configuration Word Low Field Values1805.2.5.3.2 Reduced External Reset Configuration Word High Field Values1815.2.5.4 Default Reset Configuration Words (RCW_SRC[0-2] = 100 or 101)1815.2.5.4.1 Hard Coded Reset Configuration Word Low Field Values1815.2.5.4.2 Hard Coded Reset Configuration Word High Field Values1825.3 Reset Programming Model1835.3.1 Reset Configuration Word Low Register (RCWLR)1835.3.2 Reset Configuration Word High Register (RCWHR)1855.3.3 Reset Status Register (RSR)1885.3.4 Reset Protection Register (RPR)1905.3.5 Reset Control Register (RCR)1915.3.6 Reset Control Enable Register (RCER)192Boot Program 61936.1 Functional Description1946.1.1 Private Configuration1956.1.2 Shared Configuration1956.1.3 Patch Mode1966.1.4 Multi Device Support for the I2C Bus1966.1.5 Example Configuration1986.2 Boot Modes2016.2.1 I2C EEPROM2016.2.2 Ethernet2056.2.2.1 DHCP Client2076.2.2.2 TFTP Client2086.2.2.3 Boot File Format2086.2.3 Simple Ethernet Boot2116.2.3.1 Simple Ethernet Boot Flow2116.2.3.2 Simple Ethernet Boot Ports2116.2.3.3 Boot File Format2126.2.4 Serial RapidIO Interconnect2136.2.4.1 Serial RapidIO Without I2C Support2136.2.4.2 Serial RapidIO Interface with I2C Support2146.2.5 SPI2146.3 Jump to User Code2146.4 System after Boot2156.5 Boot Errors215Clocks 72177.1 Clock Generation Components and Modes2187.2 .Programming Model2207.2.1 System Clock Control Register (SCCR)2207.2.2 Clock General Purpose Register 0 (CLK_GPR0)221General Configuration Registers 82238.1 Programming Model2238.2 Detailed Register Descriptions2248.2.1 General Configuration Register 1 (GCR1)2248.2.2 General Configuration Register 2 (GCR2)2258.2.3 General Status Register 1 (GSR1)2278.2.4 High Speed Serial Interface Status Register (HSSI_SR)2298.2.5 DDR General Control Register (DDR_GCR)2328.2.6 High Speed Serial Interface Control Register 1 (HSSI_CR1)2348.2.7 High Speed Serial Interface Control Register 2 (HSSI_CR2)2378.2.8 QUICC Engine Control Register (QECR)2388.2.9 GPIO Pull-Up Enable Register (GPUER)2398.2.10 GPIO Input Enable Register (GIER)2408.2.11 System Part and Revision ID Register (SPRIDR)2418.2.12 General Control Register 4 (GCR4)2428.2.13 General Control Register 5 (GCR5)2448.2.14 General Status Register 2 (GSR2)2468.2.15 Core Subsystem Slave Port Priority Control Register (TSPPCR)2488.2.16 QUICC Engine First External Request Multiplex Register (CPCE1R)2498.2.17 QUICC Engine Second External Request Multiplex Register (CPCE2R)2508.2.18 QUICC Engine Third External Request Multiplex Register (CPCE3R)2518.2.19 QUICC Engine Fourth External Request Multiplex Register (CPCE4R)2528.2.20 General Control Register 10 (GCR10)2538.2.21 General Interrupt Register 1 (GIR1)2548.2.22 General Interrupt Enable Register 1 (GIER1_x)2578.2.23 General Interrupt Register 3 (GIR3)2598.2.24 General Interrupt Enable Register 3 for Cores 0-3 (GIER3_x)2618.2.25 General Interrupt Register 5 (GIR5)2628.2.26 General Interrupt Enable Register 5 (GIER5_x)2648.2.27 General Control Register 11 (GCR11)2658.2.28 General Control Register 12 (GCR12)2668.2.29 DMA Request0 Control Register (GCR_DREQ0)2688.2.30 DMA Request1 Control Register (GCR_DREQ1)2728.2.31 DMA Done Control Register (GCR_DDONE)2768.2.32 DDR1 General Configuration Register (DDR1_GCR)2798.2.33 DDR2 General Configuration Register (DDR2_GCR)2808.2.34 Core Subsystem Slave Port General Configuration Register (CORE_SLV_GCR)281Memory Map 92839.1 Shared Memory Address Space2839.2 Shared SC3850 DSP Core Subsystem M2/L2 Memories2849.3 SC3850 DSP Core Subsystem Internal Address Space2859.4 CCSR Address Space2869.5 Initiators Views of the System Address Space2879.5.1 SC3850 (Data) View of the System Address Space2879.5.2 Peripherals View of the System Address Space2889.6 Detailed System Memory Map288MSC8156 SC3850 DSP Subsystem 1035910.1 SC3850 DSP Core Subsystem Features36010.2 SC3850 Core36110.3 Instruction Channel36210.3.1 Instruction Cache36210.3.2 Instruction Fetch Unit36310.4 Data Channel36310.4.1 Data Cache36310.4.2 Data Fetch Unit36410.4.3 Write-Back Buffer36510.4.4 Write-Through Buffer36510.4.5 Data Control Unit36510.4.6 Write Queue36610.5 Memory Management Unit (MMU)36610.6 L2 Cache36710.7 On-Chip Emulator and Debug and Profiling Unit36810.8 Extended Programmable Interrupt Controller36910.9 Timer36910.10 Interfaces36910.10.1 QBus to MBus Interface Bridge36910.10.2 MBus to DMA Bridge36910.11 Entering and Exiting Wait and Stop States Safely37010.11.1 Wait State37010.11.2 Stop State37010.11.2.1 Procedure for Entering DSP Subsystem Stop State Safely37010.11.2.2 Procedure for Exiting the Stop State Safely371Internal Memory Subsystem 1137311.1 Memory Management Unit (MMU)37411.2 Instruction Channel (ICache and IFU)37511.3 Data Channel and Write Queue (DCache)37711.4 L2 Unified Cache/M2 Memory38011.5 M3 Memory38411.6 Internal Boot ROM384DDR SDRAM Memory Controller 1238512.1 Features38612.2 Functional Description38712.2.1 DDR SDRAM Interface Operation39112.2.2 DDR SDRAM Organization39212.2.3 DDR SDRAM Address Multiplexing39412.3 JEDEC Standard DDR SDRAM Interface Commands39912.4 DDR SDRAM Clocking and Interface Timing40412.4.1 Clock Distribution40812.4.2 DDR SDRAM Mode-Set Command Timing40912.4.3 DDR SDRAM Registered DIMM Mode40912.4.4 DDR SDRAM Write Timing Adjustments41012.4.5 DDR SDRAM Refresh41212.4.5.1 DDR SDRAM Refresh Timing41212.4.5.2 DDR SDRAM Refresh and Power-Saving Modes41312.4.6 DDR Data Beat Ordering41512.4.7 Page Mode and Logical Bank Retention41612.5 Error Checking and Correction41612.6 Error Management41912.7 Set-Up and Initialization42012.7.1 Programming Differences Between Memory Types42412.7.2 DDR SDRAM Initialization Sequence42812.8 Memory Controller Programming Model42812.8.1 Chip-Select Bounds (MnCSx_BNDS)43012.8.2 Chip-Select x Configuration Register (MnCSx_CONFIG)43112.8.3 Chip-Select x Configuration Register 2 (MnCSx_CONFIG_2)43312.8.4 DDR SDRAM Timing Configuration 3 (MnTIMING_CFG_3)43412.8.5 DDR SDRAM Timing Configuration Register 0 (MnTIMING_CFG_0)43612.8.6 DDR SDRAM Timing Configuration Register 1 (MnTIMING_CFG_1)43912.8.7 DDR SDRAM Timing Configuration Register 2 (MnTIMING_CFG_2)44412.8.8 DDR SDRAM Control Configuration Register (MnDDR_SDRAM_CFG)44912.8.9 DDR SDRAM Control Configuration Register 2 (MnDDR_SDRAM_CFG_2)45112.8.10 DDR SDRAM Mode Configuration Register (MnDDR_SDRAM_MODE)45412.8.11 DDR SDRAM Mode Configuration 2 Register (MnDDR_SDRAM_MODE_2)45512.8.12 DDR SDRAM Mode Control Register (MnDDR_SDRAM_MD_CNTL)45512.8.13 DDR SDRAM Interval Configuration Register (MnDDR_SDRAM_INTERVAL)45812.8.14 DDR SDRAM Data Initialization Register (MnDDR_DATA_INIT)45912.8.15 DDR SDRAM Clock Control Configuration Register (MnDDR_SDRAM_CLK_CNTL)45912.8.16 DDR SDRAM Initialization Address Register (MnDDR_INIT_ADDR)46012.8.17 DDR Initialization Enable (MnDDR_INIT_EN)46112.8.18 DDR SDRAM Timing Configuration 4 (MnTIMING_CFG_4)46212.8.19 DDR SDRAM Timing Configuration 5 (MnTIMING_CFG_5)46412.8.20 DDR ZQ Calibration Control (MnDDR_ZQ_CNTL)46612.8.21 DDR Write Leveling Control (MnDDR_WRLVL_CNTL)46812.8.22 DDR Write Leveling Control 2 (MnDDR_WRLVL_CNTL_2)47112.8.23 DDR Write Leveling Control 3 (MnDDR_WRLVL_CNTL_3)47412.8.24 DDR Pre-Drive Conditioning Control (MnDDR_PD_CNTL)47712.8.25 DDR Self Refresh Counter (MnDDR_SR_CNTR)48012.8.26 DDR SDRAM Register Control Words 1 (MnDDR_SDRAM_RCW_1)48112.8.27 DDR SDRAM Register Control Words 2 (MnDDR_SDRAM_RCW_2)48212.8.28 DDR Debug Status Register 1 (MnDDRDSR_1)48312.8.29 DDR Debug Status Register 2 (MnDDRDSR_2)48412.8.30 DDR Control Driver Register 1 (MnDDRCDR_1)48412.8.31 DDR Control Driver Register 2 (MnDDRCDR_2)48812.8.32 DDR SDRAM IP Block Revision 1 Register (MnDDR_IP_REV1)48912.8.33 DDR SDRAM IP Block Revision 2 Register (MnDDR_IP_REV2)48912.8.34 DDR SDRAM Memory Data Path Error Injection Mask High Register (MnDATA_ERR_INJECT_HI)49012.8.35 DDR SDRAM Memory Data Path Error Injection Mask Low Register (MnDATA_ERR_INJECT_LO)49012.8.36 DDR SDRAM Memory Data Path Error Injection Mask ECC Register (MnERR_INJECT)49112.8.37 DDR SDRAM Memory Data Path Read Capture Data High Register (MnCAPTURE_DATA_HI)49212.8.38 DDR SDRAM Memory Data Path Read Capture Data Low Register (MnCAPTURE_DATA_LO)49212.8.39 DDR SDRAM Memory Data Path Read Capture ECC Register (MnCAPTURE_ECC)49312.8.40 DDR SDRAM Memory Error Detect Register (MnERR_DETECT)49312.8.41 DDR SDRAM Memory Error Disable Register (MnERR_DISABLE)49412.8.42 DDR SDRAM Memory Error Interrupt Enable Register (MnERR_INT_EN)49612.8.43 DDR SDRAM Memory Error Attributes Capture Register (MnCAPTURE_ATTRIBUTES)49712.8.44 DDR SDRAM Memory Error Address Capture Register (MnCAPTURE_ADDRESS)49812.8.45 DDR SDRAM Single-Bit ECC Memory Error Management Register (MnERR_SBE)49812.8.46 Debug Register 2 (MnDEBUG_2)499Interrupt Handling 1350113.1 Global Interrupt Controller (GIC)50213.2 General Configuration Block50313.2.1 Interrupt Groups50313.2.2 External Interrupts50413.2.3 Interrupt Handling50513.3 Interrupt Mapping50613.4 Core Interrupt Mesh52213.5 Programming Model52313.5.1 Global Interrupt Controller52313.5.1.1 Virtual Interrupt Generation Register (VIGR)52313.5.1.2 Virtual Interrupt Status Register (VISR)52413.5.2 General Interrupt Configuration52613.5.3 Programming Restrictions526Direct Memory Access (DMA) Controller 1452714.1 Operating Modes52814.2 Buffer Types52814.2.1 One-Dimensional Simple Buffer53014.2.2 One-Dimensional Cyclic Buffer53114.2.3 One-Dimensional Chained Buffer53214.2.4 One-Dimensional Incremental Buffer53314.2.5 One-Dimensional Complex Buffers With Dual Cyclic Buffers53414.2.6 Two-Dimensional Simple Buffer53514.2.7 Three-Dimensional Simple Buffer53714.2.8 Four-Dimensional Simple Buffer53814.2.9 Multi-Dimensional Chained Buffer54114.2.10 Two-Dimensional Cyclic Buffer54314.2.11 Three-Dimensional Cyclic Buffer54414.3 Arbitration Types54514.3.1 Round-Robin Arbitration54514.3.2 EDF Arbitration54614.3.2.1 Issuing Interrupts54714.3.2.2 Counter Control54714.3.2.3 Clock Source to the Counters54814.4 Interrupts54814.4.1 Maskable Interrupts54814.4.2 Nonmaskable Interrupts54814.5 Profiling54914.6 DMA Peripheral Interface54914.6.1 Modes of Operation54914.6.2 Configuration and Control Registers55014.6.3 Functional Description55114.6.3.1 Request Signal55114.6.3.2 Done Signal55114.6.3.3 Signal Operation55114.6.4 Using the DMA Peripheral Interface Block55214.7 DMA Programming Model55314.7.1 DMA Buffer Descriptor Base Registers x (DMABDBRx)55414.7.2 DMA Controller Channel Configuration Registers x (DMACHCRx)55514.7.3 DMA Controller Global Configuration Register (DMAGCR)55714.7.4 DMA Channel Enable Register (DMACHER)55714.7.5 DMA Channel Disable Register (DMACHDR)55814.7.6 DMA Channel Freeze Register (DMACHFR)55914.7.7 DMA Channel Defrost Register (DMACHDFR).55914.7.8 DMA Time-To-Dead Line Registers x (DMAEDFTDLx)56014.7.9 DMA EDF Control Register (DMAEDFCTRL)56114.7.10 DMA EDF Mask Register (DMAEDFMR)56114.7.11 DMA EDF Mask Update Register (DMAEDFMUR)56214.7.12 DMA EDF Status Register (DMAEDFSTR)56414.7.13 DMA Mask Register (DMAMR)56414.7.14 DMA Mask Update Register (DMAMUR)56514.7.15 DMA Status Register (DMASTR)56614.7.16 DMA Error Register (DMAERR)56714.7.17 DMA Debug Event Status Register (DMADESR)56914.7.18 DMA Local Profiling Configuration Register (DMALPCR)56914.7.19 DMA Round-Robin Priority Group Update Register (DMARRPGUR)57014.7.20 DMA Channel Active Status Register (DMACHASTR)57114.7.21 DMA Channel Freeze Status Register (DMACHFSTR)57114.7.22 DMA Channel Buffer Descriptors57114.7.22.1 Buffer Attributes (BD_ATTR)57514.7.22.2 Multi-Dimensional Buffer Attributes (BD_MD_ATTR)578High Speed Serial Interface (HSSI) Subsystem 1558315.1 HSSI Subsystem Block Diagram58415.2 OCN Fabric58515.3 DMA Controllers58615.3.1 Overview58715.3.2 Features58715.3.3 Modes of Operation58715.4 Functional Description58915.4.1 DMA Channel Operation58915.4.1.1 Source/Destination Transaction Size Calculations58915.4.1.2 Basic DMA Mode Transfer59115.4.1.2.1 Basic Direct Mode59115.4.1.2.2 Basic Direct Single-Write Start Mode59215.4.1.2.3 Basic Chaining Mode59215.4.1.2.4 Basic Chaining Single-Write Start Mode59315.4.1.2.5 Extended DMA Mode Transfer59415.4.1.3 Channel Continue Mode for Cascading Transfer Chains59515.4.1.3.1 Basic Mode59615.4.1.3.2 Extended Mode59615.4.1.4 Channel Abort59615.4.1.5 Bandwidth Control59715.4.1.6 Channel State59715.4.1.7 Illustration of Stride Size and Stride Distance59715.4.2 DMA Transfer Interfaces59815.4.3 DMA Errors59815.4.4 DMA Descriptors59915.4.5 Local Access ATMU Registers60115.4.6 Limitations and Restrictions60115.5 OCN-to-MBus (O2M) Bridges60315.6 SRIO Port Controller Modules (SRIOn)60315.7 SerDes PHY Interfaces60315.8 HSSI Programming Model60315.8.1 Mode Registers 0-3 (DnMR[0-3]).60615.8.2 Status Registers (DnSRn)60915.8.3 Current Link Descriptor Extended Address Registers (DnECLNDARn)61115.8.4 Current Link Descriptor Address Registers (DnCLNDARn):61215.8.5 Source Attributes Registers (DnSATRn)61315.8.6 Source Address Registers (DnSARn)61415.8.7 Destination Attributes Registers (DnDATRn).61515.8.8 Destination Address Registers (DnDARn)61615.8.9 Byte Count Registers (DnBCRn).61715.8.10 Extended Next Link Descriptor Address Registers (DnENLNDARn)61815.8.11 Next Link Descriptor Address Registers (DnNLNDARn)61915.8.12 Extended Current List Descriptor Address Registers (DnECLSDARn)62015.8.13 Current List Descriptor Address Registers (DnCLSDARn)62115.8.14 Extended Next List Descriptor Address Registers (DnENLSDARn)62215.8.15 Next List Descriptor Address Registers (DnNLSDARn)62315.8.16 Source Stride Registers (DnSSRn)62415.8.17 Destination Stride Registers (DnDSRn)62515.8.18 DMA General Status Register (DnDGSR))62615.8.19 Local Access Window Base Address Registers 0-9 (DnLAWBAR[0-9])62815.8.20 Local Access Window Attributes Registers 0-9 (DnLAWAR[0-9])62915.8.21 OCN-to-MBus Configuration Registers (O2MCR[0-1])63115.8.22 OCN-to-MBus Error Attribute Registers (O2MEAR[0-1])63215.8.23 OCN-to-MBus Error Address Registers (O2MEADR[0-1])63415.8.24 OCN-to-MBus Error Status Registers (O2MESR[0-1])63515.8.25 OCN-to-MBus Interrupt Enable Registers (O2MIER[0-1])63615.8.26 OCN-to-MBus Error Capture Enable Registers (O2MECER[0-1])63715.8.27 SRDS Control Register 0 (SRDSnCR0)63815.8.28 SRDS Control Register 1 (SRDSnCR1)64115.8.29 SRDS Control Register 2 (SRDSnCR2)64415.8.30 SRDS Control Register 3 (SRDSnCR3)64515.8.31 SRDS Control Register 4 (SRDSnCR4)64715.8.32 SRDS Control Register 5 (SRDSnCR5)64915.8.33 SRDS Control Register 6 (SRDSnCR6)650Serial RapidIO Controller 1665316.1 Introduction65516.1.1 Features65516.1.2 Operating Modes65716.1.3 1x/4x LP-Serial Signals65716.1.4 RapidIO Interface Activation65816.1.4.1 Initialization for Booting the MSC8156 DSP65816.1.4.2 Initialization for Non-Boot Operation65816.2 RapidIO Interface Basics65816.2.1 RapidIO Transactions65916.2.2 RapidIO Packet Format66016.2.3 RapidIO Control Symbol Summary66116.2.4 Accessing Configuration Registers via RapidIO Packets66316.2.4.1 Inbound Maintenance Accesses66316.2.4.2 RapidIO Non-Maintenance Accesses Using LCSBA1CSR66416.2.4.3 RapidIO Maintenance Accesses66416.2.4.3.1 Guidelines66416.2.4.3.2 Outbound Maintenance Accesses66416.2.5 RapidIO ATMU Implementation66516.2.5.1 RapidIO Outbound ATMU66516.2.5.2 Outbound Windows66716.2.5.3 Window Size and Segmented Windows66816.2.5.3.1 Valid Hits to Multiple ATMU Windows69216.2.5.3.2 Window Boundary Crossing Errors69316.2.5.4 RapidIO Inbound ATMU69416.2.5.4.1 Hits to Multiple ATMU Windows69616.2.5.4.2 Window Boundary Crossing Errors69616.2.6 Generating Link-Request/Reset-Device69716.2.7 Outbound Drain Mode69816.2.8 Input Port Disable Mode69916.2.9 Software Assisted Error Recovery Register Support69916.2.10 Errors and Error Handling70016.2.10.1 RapidIO Error Description70016.2.10.2 Physical Layer RapidIO Errors70216.2.10.3 Logical Layer RapidIO Errors70516.3 RapidIO Message Unit73116.3.1 Features73116.3.2 Outbound Message Controller Operation73216.3.2.1 Direct Mode73216.3.2.2 Software Error Handling73516.3.2.3 Disabling and Enabling the Message Controller73616.3.2.4 Hardware Error Handling73616.3.2.5 Chaining Mode74016.3.2.5.1 Changing Descriptor Queues in Chaining Mode74316.3.2.5.2 Preventing Queue Overflow in Chaining Mode74316.3.2.5.3 Switching Between Direct and Chaining Modes74316.3.2.5.4 Chaining Mode Descriptor Format74416.3.2.5.5 Chaining Mode Controller Interrupts74516.3.2.6 Software Error Handling74616.3.2.7 Hardware Error Handling74716.3.2.8 Outbound Message Controller Arbitration74816.3.3 Inbound Message Controller Operation74916.3.3.1 Inbound Message Controller Initialization75016.3.3.2 Inbound Controller Operation75016.3.3.3 Message Steering75216.3.3.4 Retry Response Conditions75216.3.3.5 Inbound Message Controller Interrupts75216.3.3.6 Software Error Handling75316.3.3.7 Hardware Error Handling75416.3.3.8 Programming Errors75916.3.3.9 Disabling and Enabling the Inbound Message Controller75916.3.4 RapidIO Message Passing Logical Specification Register Bits76016.4 RapidIO Doorbell76016.4.1 Features76016.4.2 Doorbell Controller76116.4.3 Outbound Doorbell Controller76216.4.3.1 Interrupts76316.4.3.2 Software Error Handling76316.4.3.3 Hardware Error Handling76416.4.3.4 Programming Errors76616.4.4 Inbound Doorbell Controller76716.4.4.1 Doorbell Queue Entry Format76816.4.4.2 Retry Response Conditions76916.4.4.3 Doorbell Controller Interrupts76916.4.4.4 Transaction Errors77016.4.4.5 Software Error Handling77016.4.4.6 Hardware Error Handling77016.4.4.7 Programming Errors77316.4.4.8 Disabling and Enabling the Doorbell Controller77416.4.4.9 RapidIO Message Passing Logical Specification Registers77416.5 Port-Write Controller77516.5.1 Port-Write Controller Initialization77516.5.2 Port-Write Controller Operation77616.5.3 Port-Write Controller Interrupts77616.5.4 Discarding Port-Writes77716.5.5 Transaction Errors77716.5.6 Software Error Handling77716.5.7 Hardware Error Handling77716.5.8 Disabling and Enabling the Port-Write Controller78016.5.9 RapidIO Message Passing Logical Specification Registers78116.6 RapidIO Programming Model78116.6.1 Device Identity Capability Register (DIDCAR)78516.6.2 Device Information Capability Register (DICAR)78516.6.3 Assembly Identity Capability Register (AIDCAR)78616.6.4 Assembly Information Capability Register (AICAR)78616.6.5 Processing Element Features Capability Register (PEFCAR)78716.6.6 Source Operations Capability Register (SOCAR)78816.6.7 Destination Operations Capability Register (DOCAR)79016.6.8 Mailbox Command and Status Register (MCSR)79116.6.9 Port Write and Doorbell Command and Status Register (PWDCSR)79316.6.10 Processing Element Logical Layer Control Command and Status Register (PELLCCSR)79416.6.11 Local Configuration Space Base Address 1 Command and Status Register (LCSBA1CSR)79516.6.12 Base Device ID Command and Status Register (BDIDCSR)79616.6.13 Host Base Device ID Lock Command and Status Register (HBDIDLCSR)79716.6.14 Component Tag Command and Status Register (CTCSR)79816.6.15 Port Maintenance Block Header 0 (PMBH0)79916.6.16 Port Link Time-Out Control Command and Status Register (PLTOCCSR)80016.6.17 Port Response Time-Out Control Command and Status Register (PRTOCCSR)80116.6.18 Port General Control Command and Status Register (PGCCSR)80216.6.19 Port 0-1 Link Maintenance Request Command and Status Register (PnLMREQCSR)80316.6.20 Port 0-1 Link Maintenance Response Command and Status Register (PnLMRESPCSR)80416.6.21 Port 0-1 Local ackID Command and Status Register (PnLASCR)80516.6.22 Port 0-1 Error and Status Command and Status Register (PnESCSR)80616.6.23 Port 0-1 Control Command and Status Register (PnCCSR)80816.6.24 Error Reporting Block Header (ERBH)81016.6.25 Logical/Transport Layer Error Detect Command and Status Register (LTLEDCSR)81016.6.26 Logical/Transport Layer Error Enable Command and Status Register (LTLEECSR)81216.6.27 Logical/Transport Layer Address Capture Command and Status Register (LTLACCSR)81316.6.28 Logical/Transport Layer Device ID Capture Command and Status Register (LTLDIDCCSR)81416.6.29 Logical/Transport Layer Control Capture Command and Status Register (LTLCCCSR)81516.6.30 Port 0-1 Error Detect Command and Status Register (PnEDCSR)81616.6.31 Port 0-1 Error Rate Enable Command and Status Register (PnERECSR)81716.6.32 Port 0-1 Error Capture Attributes Command and Status Register (PnECACSR)81816.6.33 Port 0-1 Packet/Control Symbol Error Capture Command and Status Register (PnPCSECCSR)82016.6.34 Port 0-1 Packet Error Capture Command and Status Register 1 (PnPECCSR1)82116.6.35 Port 0-1 Packet Error Capture Command and Status Register 2 (PnPECCSR2)82216.6.36 Port 0-1 Packet Error Capture Command and Status Register 3 (PnPECCSR3)82316.6.37 Port 0-1 Error Rate Command and Status Register (PnERCSR)82416.6.38 Port 0-1 Error Rate Threshold Command and Status Register (PnERTCSR)82516.6.39 Logical Layer Configuration Register (LLCR)82616.6.40 Error/Port-Write Status Register (EPWISR)82716.6.41 Logical Retry Error Threshold Configuration Register (LRETCR)82816.6.42 Physical Retry Error Threshold Configuration Register (PRETCR)82916.6.43 Port 0-1 Alternate Device ID Command and Status Register (PnADIDCSR)83016.6.44 Port 0-1 Pass-Through Accept-All Configuration Register (PnPTAACR)83116.6.45 Port 0-1 Logical Outbound Packet Time-to-Live Configuration Register (PnLOPTTLCR)83216.6.46 Port 0-1 Implementation Error Command and Status Register (PnIECSR)83316.6.47 Port 0-1 Serial Link Command and Status Register (PnSLCSR)83416.6.48 Port 0-1 Serial Link Error Injection Configuration Register (PnSLEICR)83516.6.49 IP Block Revision Register 1 (IPBRR1)83616.6.50 IP Block Revision Register 2 (IPBRR2)83616.6.51 Port 0-1 RapidIO Outbound Window Translation Address Registers x (PnROWTARx)83716.6.52 Port 0-1 RapidIO Outbound Window Translation Extended Address Registers x (PnROWTEARx)83816.6.53 Port 0-1 RapidIO Outbound Window Base Address Registers x (PnROWBARx)83916.6.54 Port 0-1 RapidIO Outbound Window Attributes Registers x (PnROWARx)84016.6.55 Port 0-1 RapidIO Outbound Window Segment 1-3 Registers 1-8 (PnROWSxRy)84216.6.56 Port 0-1 RapidIO Inbound Window Translation Address Registers x (PnRIWTARx)84316.6.57 Port 0-1 RapidIO Inbound Window Base Address Registers x (PnRIWBARx)84416.6.58 Port 0-1 RapidIO Inbound Window Attributes Registers x (PnRIWARx)84516.6.59 Outbound Message x Mode Registers (OMxMR)84616.6.60 Outbound Message x Status Registers (OMxSR)84816.6.61 Outbound Message x Descriptor Queue Dequeue Pointer Address Registers (DMxDQDPAR)85016.6.62 Outbound Message x Source Address Registers (OMxSAR)85116.6.63 Outbound Message x Destination Port Register (OMxDPR)85216.6.64 Outbound Message x Destination Attributes Register (OMxDATR)85316.6.65 Outbound Message x Double-Word Count Register (DMxDCR)85416.6.66 Outbound Message x Descriptor Queue Enqueue Pointer Address Registers (OMxDQEPAR)85516.6.67 Outbound Message x Retry Error Threshold Configuration Register (OMxRETCR)85616.6.68 Outbound Message x Multicast Group Registers (OMxMGR)85716.6.69 Outbound Message x Multicast List Registers (OMxMLR)85816.6.70 Inbound Message x Mode Registers (IMxMR)85916.6.71 Inbound Message x Status Registers (IMxSR)86116.6.72 Inbound Message x Frame Queue Dequeue Pointer Address Registers (IMxFQDPAR)86316.6.73 Inbound Message x Frame Queue Enqueue Pointer Address Registers (IMxFQEPAR)86416.6.74 Inbound Message x Maximum Interrupt Report Interval Registers (IMxMIRIR)86516.6.75 Outbound Doorbell Mode Register (ODMR)86616.6.76 Outbound Doorbell Status Register (ODSR)86716.6.77 Outbound Doorbell Destination Port Register (ODDPR)86816.6.78 Outbound Doorbell Destination Attributes Register (ODDATR)86916.6.79 Outbound Doorbell Retry Error Threshold Configuration Register (ODRETCR)87016.6.80 Inbound Doorbell Mode Registers (IDMR)87116.6.81 Inbound Doorbell Status Register (IDSR)87316.6.82 Inbound Doorbell Queue Dequeue Pointer Address Register (IDQDPAR)87416.6.83 Inbound Doorbell Queue Enqueue Pointer Address Registers (IDQEPAR)87516.6.84 Inbound Doorbell Maximum Interrupt Report Interval Register (IDMIRIR)87616.6.85 Inbound Port-Write Mode Register (IPWMR)87716.6.86 Inbound Port-Write Status Register (IPWSR)87816.6.87 Inbound Port-Write Queue Base Address Register (IPWQBAR)879PCI Express Controller 1788117.1 Overview88117.1.1 Outbound Transactions88217.1.2 Inbound Transactions88317.2 Features88417.3 Functional Description88517.3.1 Modes of Operation88617.3.2 PCI Express Transactions88617.3.2.1 Byte Ordering88717.3.2.2 Byte Order for Configuration Transactions88917.3.2.3 Transaction Ordering Rules88917.3.2.4 Memory Space Addressing89017.3.2.5 I/O Space Addressing89017.3.2.6 Configuration Space Addressing89117.3.2.7 Serialization of Configuration and I/O Writes89117.3.3 Messages89117.3.3.1 Outbound ATMU Message Generation89217.3.3.2 Inbound Messages89317.3.4 Error Handling89517.3.4.1 PCI Express Error Logging and Signaling89517.3.4.2 PCI Express Controller Internal Interrupt Sources89717.3.4.3 Error Conditions89817.3.5 Interrupts90117.3.6 Initial Credit Advertisement90217.3.7 Power Management90217.3.8 L2/L3 Ready Link State90317.3.9 Hot Reset90317.3.10 Link Down90417.3.11 Initialization/Application Information90417.4 Programming Model90417.4.1 PCI Express Memory Mapped Registers90517.4.1.1 PCI Express Configuration Access Registers90717.4.1.1.1 PCI Express Configuration Address Register (PEX_CONFIG_ADDR)90717.4.1.1.2 PCI Express Configuration Data Register (PEX_CONFIG_DATA)90817.4.1.1.3 PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)90917.4.1.1.4 PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR)91017.4.1.1.5 PCI Express Configuration Register (PEX_CONFIG)91017.4.1.2 PCI Express Power Management Event and Message Registers91117.4.1.2.1 PCI Express PME and Message Detect Register (PEX_PME_MES_DR)91117.4.1.2.2 PCI Express PME and Message Disable Register (PEX_PME_MES_DISR)91317.4.1.2.3 PCI Express PME and Message Interrupt Enable Register (PEX_PME_MES_IER)91417.4.1.2.4 PCI Express Power Management Command Register (PEX_PMCR)91617.4.1.2.5 PCI Express Link Width Control Register (PEX_LWCR)91717.4.1.2.6 PCI Express Link Width Status Register (PEX_LWSR)91817.4.1.2.7 PCI Express Link Speed Control Register (PEX_LSCR)91917.4.1.2.8 PCI Express Link Speed Status Register (PEX_LSSR)92017.4.1.3 PCI Express IP Block Revision Registers92117.4.1.3.1 IP Block Revision Register 1 (PEX_IP_BLK_REV1)92117.4.1.3.2 IP Block Revision Register 2 (PEX_IP_BLK_REV2)92117.4.1.4 PCI Express ATMU Registers92217.4.1.4.1 PCI Express Outbound ATMU Registers92217.4.1.4.2 PCI Express Outbound Translation Address Registers (PEXOTARn)92217.4.1.4.3 PCI Express Outbound Translation Extended Address Registers (PEXOTEARn)92317.4.1.4.4 PCI Express Outbound Window Base Address Registers (PEXOWBARn)92417.4.1.4.5 PCI Express Outbound Window Attributes Registers (PEXOWARn)92517.4.1.4.6 PCI Express Inbound ATMU Registers92717.4.1.4.7 EP Inbound ATMU Implementation92717.4.1.4.8 RC Inbound ATMU Implementation92717.4.1.4.9 PCI Express Inbound Translation Address Registers (PEXITARn)92817.4.1.4.10 PCI Express Inbound Window Base Address Register 1 (PEXIWBAR1)92917.4.1.4.11 PCI Express Inbound Window Base Address Registers (PEXIWBARn)93017.4.1.4.12 PCI Express Inbound Window Base Extended Address Registers (PEXIWBEARn)93117.4.1.4.13 PCI Express Inbound Window Attributes Registers (PEXIWARn)93217.4.1.5 PCI Express Error Management Registers93417.4.1.5.1 PCI Express Error Detect Register (PEX_ERR_DR)93417.4.1.5.2 PCI Express Error Interrupt Enable Register (PEX_ERR_EN)93617.4.1.5.3 PCI Express Error Disable Register (PEX_ERR_DISR)93817.4.1.5.4 PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)93917.4.1.5.5 PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)94017.4.1.5.6 PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)94117.4.1.5.7 PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)94317.4.1.5.8 PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3)94417.4.1.6 PCI Express Configuration Space Access94517.4.1.6.1 RC Configuration Register Access94517.4.1.6.2 PCI Express Configuration Access Register Mechanism94617.4.1.6.3 Outbound ATMU Configuration Mechanism (RC-Only)94617.4.1.6.4 EP Configuration Register Access94717.4.1.7 PCI Compatible Configuration Headers94717.4.1.7.1 Common PCI Compatible Configuration Header Registers94717.4.1.7.2 PCI Express Vendor ID Register-Offset 0x0094817.4.1.7.3 PCI Express Device ID Register-Offset 0x0294817.4.1.7.4 PCI Express Command Register-Offset 0x0494817.4.1.7.5 PCI Express Status Register-Offset 0x0695017.4.1.7.6 PCI Express Revision ID Register-Offset 0x0895117.4.1.7.7 PCI Express Class Code Register-Offset 0x0995117.4.1.7.8 PCI Express Cache Line Size Register-Offset 0x0C95217.4.1.7.9 PCI Express Latency Timer Register-0x0D95217.4.1.7.10 PCI Express Header Type Register-0x0E95317.4.1.7.11 PCI Express BIST Register-0x0F95317.4.1.7.12 Type 0 Configuration Header95317.4.1.7.13 PCI Express Base Address Registers-0x10-0x2795417.4.1.7.14 PCI Express Subsystem Vendor ID Register (EP-Mode Only)-0x2C95617.4.1.7.15 PCI Express Subsystem ID Register (EP-Mode Only)-0x2E95717.4.1.7.16 Capabilities Pointer Register-0x3495717.4.1.7.17 PCI Express Interrupt Line Register (EP-Mode Only)-0x3C95817.4.1.7.18 PCI Express Interrupt Pin Register-0x3D95817.4.1.7.19 PCI Express Minimum Grant Register (EP-Mode Only)-0x3E95817.4.1.7.20 PCI Express Maximum Latency Register (EP-Mode Only)-0x3F95917.4.1.7.21 Type 1 Configuration Header95917.4.1.7.22 PCI Express Base Address Register 0-0x1096017.4.1.7.23 PCI Express Primary Bus Number Register-Offset 0x1896017.4.1.7.24 PCI Express Secondary Bus Number Register-Offset 0x1996117.4.1.7.25 PCI Express Subordinate Bus Number Register-Offset 0x1A96117.4.1.7.26 PCI Express Secondary Latency Timer Register-0x1B96117.4.1.7.27 PCI Express I/O Base Register-0x1C96217.4.1.7.28 PCI Express I/O Limit Register-0x1D96217.4.1.7.29 PCI Express Secondary Status Register-0x1E96317.4.1.7.30 PCI Express Memory Base Register-0x2096417.4.1.7.31 PCI Express Memory Limit Register-0x2296417.4.1.7.32 PCI Express Prefetchable Memory Base Register-0x2496517.4.1.7.33 PCI Express Prefetchable Memory Limit Register-0x2696517.4.1.7.34 PCI Express Prefetchable Base Upper 32 Bits Register-0x2896617.4.1.7.35 PCI Express Prefetchable Limit Upper 32 Bits Register-0x2C96617.4.1.7.36 PCI Express I/O Base Upper 16 Bits Register-0x3096717.4.1.7.37 PCI Express I/O Limit Upper 16 Bits Register-0x3296717.4.1.7.38 Capabilities Pointer Register-0x3496817.4.1.7.39 PCI Express Interrupt Line Register-0x3C96817.4.1.7.40 PCI Express Interrupt Pin Register-0x3D96817.4.1.7.41 PCI Express Bridge Control Register-0x3E96917.4.1.8 PCI Compatible Device-Specific Configuration Space97017.4.1.8.1 PCI Express Power Management Capability ID Register-0x4497117.4.1.8.2 PCI Express Power Management Capabilities Register-0x4697117.4.1.8.3 PCI Express Power Management Status and Control Register-0x4897217.4.1.8.4 PCI Express Power Management Data Register-0x4B97217.4.1.8.5 PCI Express Capability ID Register-0x4C97317.4.1.8.6 PCI Express Capabilities Register-0x4E97317.4.1.8.7 PCI Express Device Capabilities Register-0x5097417.4.1.8.8 PCI Express Device Control Register-0x5497517.4.1.8.9 PCI Express Device Status Register-0x5697517.4.1.8.10 PCI Express Link Capabilities Register-0x5897617.4.1.8.11 PCI Express Link Control Register-0x5C97617.4.1.8.12 PCI Express Link Status Register-0x5E97717.4.1.8.13 PCI Express Slot Capabilities Register-0x6097717.4.1.8.14 PCI Express Slot Control Register-0x6497817.4.1.8.15 PCI Express Slot Status Register-0x6697917.4.1.8.16 PCI Express Root Control Register (RC Mode Only)-0x6897917.4.1.8.17 PCI Express Root Status Register (RC Mode Only)-0x6C98017.4.1.8.18 PCI Express MSI Message Capability ID Register (EP Mode Only)-0x7098017.4.1.8.19 PCI Express MSI Message Control Register (EP Mode Only)-0x7298117.4.1.8.20 PCI Express MSI Message Address Register (EP Mode Only)-0x7498117.4.1.8.21 PCI Express MSI Message Upper Address Register (EP Mode Only)-0x7898217.4.1.8.22 PCI Express MSI Message Data Register (EP Mode Only)-0x7C98217.4.1.9 PCI Express Extended Configuration Space98317.4.1.9.1 PCI Express Advanced Error Reporting Capability ID Register-0x10098417.4.1.9.2 PCI Express Uncorrectable Error Status Register-0x10498417.4.1.9.3 PCI Express Uncorrectable Error Mask Register-0x10898517.4.1.9.4 PCI Express Uncorrectable Error Severity Register-0x10C98617.4.1.9.5 PCI Express Correctable Error Status Register-0x11098717.4.1.9.6 PCI Express Correctable Error Mask Register-0x11498817.4.1.9.7 PCI Express Advanced Error Capabilities and Control Register-0x11898917.4.1.9.8 PCI Express Header Log Register-0x11C-0x12B99017.4.1.9.9 PCI Express Root Error Command Register-0x12C99117.4.1.9.10 PCI Express Root Error Status Register-0x13099117.4.1.9.11 PCI Express Correctable Error Source ID Register-0x13499217.4.1.9.12 PCI Express Error Source ID Register-0x13699217.4.1.9.13 LTSSM State Control Register-0x40099317.4.1.9.14 LTSSM State Status Register-0x40499417.4.1.9.15 PCI Express ACK Replay Timeout Register (PEX_ACK_REPLAY_TIMEOUT)-0x43499617.4.1.9.16 PCI Express Controller Core Clock Ratio Register-0x44099717.4.1.9.17 PCI Express Power Management Timer Register-0x45099717.4.1.9.18 PCI Express PME Time-Out Register (EP-Mode Only)-0x45499817.4.1.9.19 PCI Express Subsystem Vendor ID Update Register (EP Mode Only)-0x47899917.4.1.9.20 Configuration Ready Register-0x4B099917.4.1.9.21 PME_To_Ack Timeout Register (RC-Mode Only)-0x590100017.4.1.9.22 Secondary Status Interrupt Mask Register (RC-Mode Only)-0x5A0100117.4.1.9.23 Gen2 Control Register1002QUICC Engine Subsystem 18100318.1 Overview100418.2 RISC Processors100518.2.1 SC3850 Core Interface100518.2.2 Peripheral Interface100618.2.3 Parameter RAM100618.2.4 Buffer Descriptors (BDs)100718.2.5 Multithreading100818.2.6 Serial Numbers (SNUMs)100918.2.7 IRAM101018.3 Serial DMA Controller101018.3.1 Data Paths101018.3.2 SDMA and Bus Error101118.3.2.1 Simple Recovery from Bus Error101118.3.2.2 Selective Peripheral Recovery Procedure101218.3.3 SDMA and Reset101218.3.4 MBus Access101218.3.5 SDMA Internal Resource101318.4 Clocking101318.4.1 Multiplexer Logic101318.4.2 Baud-Rate Generators (BRGs)101518.5 Interrupt Controller101618.6 UCCs101618.7 Ethernet Controllers101818.7.1 Operating Modes102018.7.1.1 RGMII Mode102018.7.1.2 SGMII Mode102018.7.2 Ethernet Physical Interfaces102018.7.2.1 Reduced Gigabit Media-Independent Interface (RGMII) Signals102118.7.2.1.1 RGMII Signals102118.7.2.1.2 RGMII Signal Configuration102218.7.2.2 Serial Gigabit Media-Independent Interface (SGMII) Signals102218.7.2.2.1 SGMII Signals102318.7.2.2.2 SGMII Signal Configuration102318.7.3 Controlling PHY Links (Management Interface)102418.7.4 Ethernet Controller Initialization102418.8 Serial Peripheral Interface (SPI)102518.8.1 SPI Operating Modes102618.8.1.1 SPI as a Master Device102618.8.1.2 SPI as a Slave Device102818.8.2 SPI in Multi-Master Operation102818.8.3 External Signal Configuration103018.8.4 SPI Transmission and Reception Process103018.9 Programming Model1031TDM Interface 19103719.1 Typical Configurations104119.2 TDM Basics104219.2.1 Common Signals for the TDM Modules104419.2.2 Receiver and Transmitter Independent or Shared Operation104619.2.3 TDM Data Structures104919.2.4 Serial Interface105119.2.4.1 Sync Out Configuration105119.2.4.2 Sync In Configuration105219.2.4.3 Serial Interface Synchronization105419.2.4.4 Reverse Data Order105619.2.5 TDM Local Memory105819.2.6 Buffers Mapped on System Memory105919.2.6.1 Data Buffer Size and A/m-law Channels105919.2.6.2 Data Buffer Address106019.2.6.3 Threshold Pointers and Interrupts106219.2.6.4 Unified Buffer Mode106419.2.7 Adaptation Machine106619.3 TDM Power Saving106719.4 Channel Activation106719.5 Loopback Support106819.6 TDM Initialization106919.7 TDM Programming Model107019.7.1 Configuration Registers107219.7.1.1 TDMx General Interface Register (TDMxGIR)107219.7.1.2 TDMx Receive Interface Register (TDMxRIR)107919.7.1.3 TDMx Transmit Interface Register (TDMxTIR)108119.7.1.4 TDMx Receive Frame Parameters (TDMxRFP)108319.7.1.5 TDMx Transmit Frame Parameters (TDMxTFP)108619.7.1.6 TDMx Receive Data Buffer Size (TDMxRDBS)108819.7.1.7 TDMx Transmit Data Buffer Size (TDMxTDBS)108919.7.1.8 TDMx Receive Global Base Address108919.7.1.9 TDMx Transmit Global Base Address109019.7.1.10 TDMx Transmit Force Register (TDMxTFR)109019.7.1.11 TDMx Receive Force Register (TDMxRFR)109119.7.1.12 TDMx Parity Control Register (TDMxPCR)109219.7.2 Control Registers109219.7.2.1 TDMx Adaptation Control Register109219.7.2.2 TDMx Receive Control Register109319.7.2.3 TDMx Transmit Control Register (TDMxTCR)109419.7.2.4 TDMx Receive Data Buffer First Threshold (TDMxRDBFT)109419.7.2.5 TDMx Transmit Data Buffer First Threshold109519.7.2.6 TDMx Receive Data Buffer Second Threshold109619.7.2.7 TDMx Transmit Data Buffer Second Threshold109619.7.2.8 TDMx Receive Channel Parameter Register n109719.7.2.9 TDMx Transmit Channel Parameter Register n109819.7.2.10 TDMx Receive Interrupt Enable Register (TDMXRIER)109919.7.2.11 TDMx Transmit Interrupt Enable Register (TDMxTIER)110019.7.3 Status Registers110119.7.3.1 TDMx Adaptation Sync Distance Register (TDMxASDR)110119.7.3.2 TDMx Receive Data Buffers Displacement Register (TDMxRDBDR)110219.7.3.3 TDMx Transmit Data Buffer Displacement Register (TDMxTDBDR)110219.7.3.4 TDMx Receive Number of Buffers (TDMxRNB)110319.7.3.5 TDMx Transmitter Number of Buffers (TDMxTNB)110419.7.3.6 TDMx Receive Event Register (TDMxRER)110419.7.3.7 TDMx Transmit Event Register (TDMxTER)110519.7.3.8 TDMx Adaptation Status Register (TDMxASR)110619.7.3.9 TDMx Receive Status Register (TDMxRSR)110719.7.3.10 TDMx Transmit Status Register (TDMxTSR)110819.7.3.11 TDMx Parity Error Register (TDMxPER)1109UART 20111120.1 Transmitter111620.1.1 Character Transmission111720.1.2 Break Characters111920.1.3 Idle Characters112020.1.4 Parity Bit Generation112020.2 Receiver112020.2.1 Character Reception112120.2.2 Data Sampling112220.2.3 Framing Error112720.2.4 Parity Error112820.2.5 Break Characters112820.2.6 Baud-Rate Tolerance112820.2.6.1 Slow Data Tolerance112920.2.6.2 Fast Data Tolerance113020.2.7 Receiver Wake-Up113020.2.7.1 Idle Input Line Wake-Up (WAKE = 0)113120.2.7.2 Address Mark Wake-Up (WAKE = 1)113120.3 Reset Initialization113120.4 Modes of Operation113220.4.1 Run Mode113220.4.2 Single-Wire Operation113220.4.3 Loop Operation113320.4.4 Stop Mode113320.4.5 Receiver Standby Mode113320.5 Interrupt Operation113420.6 UART Programming Model113420.6.1 SCI Baud-Rate Register (SCIBR)113520.6.2 SCI Control Register (SCICR)113620.6.3 SCI Status Register (SCISR)113920.6.4 SCI Data Register (SCIDR)114120.6.5 SCI Data Direction Register (SCIDDR)1142Timers 21114321.1 Device-Level Timers114321.1.1 Features114421.1.2 Timer Module Architecture114421.1.3 Setting Up Counters for Cascaded Operation114521.1.3.1 Operation of the Cascaded Timer114621.1.3.2 Cascading Restrictions114621.1.4 Timer Operating Modes114721.1.4.1 One-Shot Mode114921.1.4.2 Pulse Output Mode114921.1.4.3 Fixed Frequency PWM Mode114921.1.4.4 Variable Frequency PWM Mode115021.1.5 Timer Compare Functionality115221.1.5.1 Compare Preload Registers115321.1.5.2 Capture Register Use115321.1.5.3 Broadcast from an Initiator Timer115421.1.6 Resets and Interrupts115421.1.6.1 Timer Compare Interrupts115421.1.6.2 Timer Overflow Interrupts115521.1.6.3 Timer Input Edge Interrupts115521.2 SC3850 DSP Core Subsystem Timers115521.3 Software Watchdog Timers115521.3.1 Features115621.3.2 Modes of Operation115621.3.3 Software WDT Servicing115721.4 Timers Programming Model115821.4.1 Device-Level Timers115821.4.1.1 Timer Channel Control Registers (TMRnCTLx)115921.4.1.2 Timer Channel Status and Control Registers (TMRnSCTLx)116121.4.1.3 Timer Channel Compare 1 Registers (TMRnCMP1x)116321.4.1.4 Timer Channel Compare 2 Registers (TMRnCMP2x)116321.4.1.5 Timer Channel Compare Load 1 Registers (TMRnCMPLD1x)116421.4.1.6 Timer Channel Compare Load 2 Registers (TMRnCMPLD2x)116421.4.1.7 Timer Channel Comparator Status and Control Registers (TMRnCOMSCx)116421.4.1.8 Timer Channel Capture Registers (TMRnCAPx)116521.4.1.9 Timer Channel Load Registers (TMRnLOADx)116621.4.1.10 Timer Channel Hold Registers (TMRnHOLDx)116621.4.1.11 Timer Channel Counter Registers (TMRnCNTRx)116621.4.2 SC3850 DSP Core Subsystem Timers116621.4.3 Software Watchdog Timers116721.4.3.1 System Watchdog Control Register 0-7 (SWCRR[0-7])116821.4.3.2 System Watchdog Count Register 0-7 (SWCNR[0-7])116921.4.3.3 System Watchdog Service Register 0-7 (SWSRR[0-7])1169GPIO 22117122.1 Features117122.2 GPIO Block Diagram117222.3 GPIO Connection Functions117322.4 GPIO Programming Model117522.4.1 Pin Open-Drain Register (PODR)117622.4.2 Pin Data Register (PDAT)117722.4.3 Pin Data Direction Register (PDIR)117822.4.4 Pin Assignment Register (PAR)117922.4.5 Pin Special Options Register (PSOR)1180Hardware Semaphores 231181I2C 24118324.1 Features118424.2 Modes of Operation118424.3 I2C Module Functional Blocks118524.3.1 Clock Control118524.3.2 Input Synchronization118524.3.3 Digital Input Filter118524.3.4 Transaction Monitoring118624.3.5 Arbitration Control118624.3.6 Transfer Control118624.3.7 In/Out Data Shift Register118724.3.8 Address Compare118724.4 Functional Description118824.4.1 START Condition118824.4.2 Target Address Transmission118924.4.3 Repeated START Condition118924.4.4 STOP Condition119024.4.5 Arbitration Procedure119024.4.6 Clock Synchronization119124.4.7 Handshaking119124.4.8 Clock Stretching119124.5 Initialization/Application Information119124.5.1 Initialization Sequence119224.5.2 Generation of START119224.5.3 Post-Transfer Software Response119224.5.4 Generation of STOP119324.5.5 Generation of Repeated START119324.5.6 Generation of I2C_SCL When I2C_SDA Low119324.5.7 Target Mode Interrupt Service Routine119424.5.8 Target Transmitter and Received Acknowledge119424.5.9 Loss of Arbitration and Forcing of Target Mode119424.5.10 Interrupt Service Routine Flowchart119424.6 Programming Model119624.6.1 I2C Address Register (I2CADR)119624.6.2 I2C Frequency Divider Register (I2CFDR)119724.6.3 I2C Control Register (I2CCR)119824.6.4 I2C Status Register (I2CSR)119924.6.5 I2C Data Register (I2CDR)120124.6.6 Digital Filter Sampling Rate Register (I2CDFSRR)1201Debugging, Profiling, and Performance Monitoring 25120325.1 TAP, Boundary Scan, and OCE120325.1.1 Overview120425.1.2 TAP Controller120725.1.3 Instruction Decoding120825.1.4 Multi-Core JTAG and OCE Module Concept121225.1.5 Enabling the OCE Module121225.1.6 DEBUG_REQUEST and ENABLE_ONCE Commands121325.1.7 RD_STATUS Command121425.1.8 Reading/Writing OCE Registers Through JTAG121425.1.9 Signalling a Debug Request121525.1.10 EE_CTRL Modifications for the MSC8156121625.1.11 ESEL_DM and EDCA_CTRL Register Programming121725.1.12 Real-Time Debug Request121725.1.13 Exiting Debug Mode121825.1.14 General JTAG Mode Restrictions121925.1.15 JTAG and OCE Module Programming Model121925.1.15.1 Identification Register121925.1.15.2 Boundary Scan Register (BSR)122025.1.15.3 Shift Registers122225.1.15.4 Bypass Register122225.1.15.5 Identification Register122325.2 Debug and Profiling122425.2.1 Features122425.2.2 Entering Debug Mode122525.2.3 Exiting Debug mode122525.2.4 SC3850 Debug and Profiling122625.2.5 L1 ICache and DCache Debug and Profiling122625.2.6 DMA Controller Debug and Profiling122625.2.6.1 Debug Errors122625.2.6.2 Profiling Unit122725.2.7 CLASS Modules122725.2.7.1 Debug122725.2.7.2 CLASS Debug Profiling Unit (CDPU)122725.2.8 QUICC Engine Debug and Profiling122925.2.8.1 Trace Buffer122925.2.8.2 Loopback Modes122925.2.9 TDM Debug and Profiling123025.2.9.1 Debug123025.2.9.2 TDM Loopback Support123025.2.10 RapidIO Debug and Profiling123025.2.10.1 Debug Errors123025.2.10.2 Profiling Unit123125.2.11 MAPLE-B Debug123125.2.12 Software Watchdog (SWT)123125.2.13 Profiling Unit Programming Model123125.2.13.1 DPU Control Register (DP_CR)123325.2.13.2 DPU Status Register (DP_SR)123525.2.13.3 DPU Monitor Register (DP_MR)123625.2.13.4 DPU PID Detection Reference Value Register (DP_RPID)123725.2.13.5 DPU DID Detection Reference Value Register (DP_RDID)123825.2.13.6 DPU Counter Triad A Control Register (DP_TAC)123825.2.13.7 DPU Counter Triad B Control Register (DP_TBC)124225.2.13.8 DPU Counter A0 Control Register (DP_CA0C)124425.2.13.9 DPU Counter A0 Value Register (DP_CA0V)124625.2.13.10 DPU Counter A1 Control Register (DP_CA1C)124725.2.13.11 DPU Counter A1 Value Registers (DP_CA1V)124925.2.13.12 DPU Counter A2 Control Register (DP_CA2C)124925.2.13.13 DPU Counter A2 Value Registers (DP_CA2V)125225.2.13.14 DPU Counter B0 Control Register (DP_CB0C)125225.2.13.15 DPU Counter B0 Value Registers (DP_CB0V)125525.2.13.16 DPU Counter B1 Control Register (DP_CB1C)125525.2.13.17 DPU Counter B1 Value Registers (DP_CB1V)125825.2.13.18 DPU Counter B2 Control Register (DP_CB2C)125825.2.13.19 DPU Counter B2 Value Registers (DP_CB2V)126125.2.13.20 DPU Trace Control Register (DP_TC)126125.2.13.21 DPU VTB Start Address Register (DP_TSA)126525.2.13.22 DPU VTB End Address Register (DP_TEA)126625.2.13.23 DPU Trace Event Request Register (DP_TER)126725.2.13.24 DPU Trace Write Pointer Register (DP_TW)126825.2.13.25 DPU Trace Data Register (DP_TD)126925.3 Performance Monitor126925.3.1 Functional Description127125.3.1.1 Performance Monitor Interrupts127125.3.1.2 Event Counting127125.3.1.3 Threshold Events127225.3.1.4 Chaining127225.3.1.5 Performance Monitor Events127325.3.1.6 Performance Monitor Examples127925.3.2 Performance Monitor Programming Model128125.3.2.1 Performance Monitor Global Control Register (PMGC)128225.3.2.2 Performance Monitor Local Control A0 Register (PMLCA0)128325.3.2.3 Performance Monitor Local Control A[1-8] (PMLCA[1-8])128425.3.2.4 Performance Monitor Local Control B[1-8] (PMLCB[1-8])128525.3.2.5 Performance Monitor Counter 0 (PMC0)128625.3.2.6 Performance Monitor Counter 1-8 (PMC[1-8])1287Multi Accelerator Platform Engine, Baseband (MAPLE-B) 26128926.1 Features129026.2 Modes of Operation129326.2.1 3GLTE Standard Operation Mode129326.2.2 WiMAX Standard Operation Mode129326.2.3 3GPP Standard Operation Mode129426.2.4 3GPP2 Standard Operation Mode129426.3 Functional Description129426.3.1 Buffer Descriptors (BDs)129426.3.1.1 BD Rings Arbitration129426.3.1.2 BD Arbitration129626.3.1.3 BDs Data Coherency Bit129826.3.1.4 Turbo/Viterbi Decoding Flow129926.3.1.4.1 Turbo Standard Parameter Assumptions129926.3.1.4.2 TVPE Buffer-Descriptor Structure130026.3.1.4.3 Buffer Descriptor Special Notes131226.3.1.4.4 TVPE Input Data Structures131226.3.1.4.5 Input Sample Polarity131326.3.1.4.6 Direct Data Structure131426.3.1.4.6.1 3GLTE and 3GPP Operation Modes-Rate 1/3 Turbo Processing131426.3.1.4.6.2 3GPP2 Operation Mode-Rate 1/5 Turbo Processing131726.3.1.4.6.3 WiMAX Turbo Processing Operation Mode132026.3.1.4.6.4 Viterbi Processing132126.3.1.4.7 Separate Vectors Data Structure132426.3.1.4.7.1 Zero Tail Identification for Separate Vectors132526.3.1.4.7.2 BD Pointers Allocation for Separate Vectors Data Structure132726.3.1.4.8 Periodically Punctured Configurable Mix Stream (PPCMS) Data Structure132726.3.1.4.8.1 Zero Tail Identification for PPCMS133126.3.1.4.8.2 BD Pointers Allocation for PPCMS133126.3.1.4.9 Rate-Matched Fixed Mix Stream Data Structure133226.3.1.4.9.1 Rate De-Matching Using De-Puncturing133326.3.1.4.9.2 Rate De-Matching Using De-Repetition133526.3.1.4.9.3 Zero Tail Identification for Rate-Matched Fixed Mix Stream133626.3.1.4.9.4 BD Pointers Allocation for Rate-Matched Fixed Mix Stream133626.3.1.4.10 Sub-Block Interleaved Vectors Data Structure133726.3.1.4.10.1 Zero Tail identification for Sub-Block Interleaved Vectors133926.3.1.4.10.2 BD Pointers Allocation for Sub-Block Interleaved Vectors Data Structure133926.3.1.4.11 Supported Input Data Structures for Different Standards134026.3.1.4.11.1 3GPP2 Operation Mode-Large Blocks Treatment134026.3.1.4.11.2 3GLTE Supported Block Sizes (BS)134126.3.1.4.11.3 Expected Vectors Example for 3GLTE Separate Vectors134126.3.1.4.12 Adjacent Bit Description ([ADJ])134226.3.2 PE Operations134326.3.2.1 Turbo/Viterbi PE134326.3.2.1.1 Turbo Decoding Processing134326.3.2.1.1.1 Turbo Channel Data Interleaving134326.3.2.1.1.2 Number of Turbo Processing Elements (DREs)134426.3.2.1.1.3 Turbo Processing Implementation134526.3.2.1.1.4 CRC Check134626.3.2.1.1.5 Stopping Criteria134726.3.2.1.2 Viterbi Decoding Operation135226.3.2.1.2.1 Viterbi Processing-General135226.3.2.1.2.2 Zero Tail Viterbi Processing135626.3.2.1.2.3 Tail Biting Viterbi Processing (WAVA*)135626.3.2.1.2.4 Viterbi Large Blocks Partitioning Support135726.3.2.1.3 TVPE Output Data136126.3.2.1.3.1 Output Data Types136126.3.2.1.3.2 Soft/Extrinsic Output Data136126.3.2.1.3.3 Hard Output Data136426.3.2.1.4 Output Data Structure136526.3.2.1.4.1 Byte Ordering136526.3.2.1.4.2 Bit Ordering136626.3.2.1.4.3 Byte/Bit Ordering Limitations136626.3.2.1.5 TVPE Debug and Profiling136626.3.2.1.5.1 TVPE Debug136626.3.2.1.5.2 TVPE Profiling136726.3.2.2 FFT/iFFT/DFT/iDFT Operation136826.3.2.2.1 FTPE Buffer-Descriptor Structure136826.3.2.2.1.1 BD Repeat Option137626.3.2.2.1.2 Buffer Descriptors Notes137826.3.2.2.2 FTPE Data Structures137826.3.2.2.2.1 Input Data Structure137826.3.2.2.2.2 Guard Band Insertion for iFFT138026.3.2.2.2.3 Output Data Structure.138126.3.2.2.2.4 Pre-Multiplication Support for FFT/iFFT Processing in the FFTPE138126.3.2.2.3 FTPE Processing138326.3.2.2.3.1 FTPE Algorithm138326.3.2.2.3.2 Inverse Transform Processing138726.3.2.2.3.3 Transform Length Partitioning138726.3.2.2.3.4 Scaling138926.3.2.2.4 FTPE Status Indications139326.3.2.2.5 Using the DFTPE as FFTPE139326.3.2.2.6 FTPE Profiling139426.3.2.3 CRC Operation139526.3.2.3.1 CRC Buffer-Descriptor Structure139526.3.2.3.2 Buffer Descriptors Notes139926.3.2.3.3 CRC Input Data Structure139926.3.2.3.4 CRC Processing140126.3.2.3.4.1 Byte Reverse CRC Processing140126.3.2.3.4.2 CRC Init value140126.3.2.3.4.3 CRC Polynomials140226.3.2.3.5 CRC Processing Results140226.3.2.3.5.1 Reverse Output Operation140226.3.2.3.5.2 Inverse Output Operation140226.3.2.3.5.3 CRC Result Check/Calculate140326.3.3 :System Interface140326.3.3.1 Error Correction Code (ECC) Memory Support140326.3.3.2 Interrupts140426.3.3.2.1 BD Rings Done Indication Interrupts140426.3.3.2.2 General Error Event Interrupt140526.3.3.2.3 ECC Error Interrupts140526.3.3.3 External Masters Support Using Serial RapidIO Doorbell140626.3.3.3.1 Serial RapidIO Doorbell Parameters Configuration140626.3.3.3.2 Serial RapidIO Configuration Information140726.3.3.4 Operation Flow140826.3.3.5 MAPLE-B Internal Task Control140926.3.3.6 Power Save141026.3.3.7 Reset141026.3.3.7.1 External Hard/Soft Reset141026.3.3.7.2 Internal Soft Reset141126.3.4 Initialization Information141126.4 Programming Model141226.4.1 Memory Map141326.4.1.1 MAPLE-B Parameter RAM141326.4.1.2 TVPE Registers141626.4.1.3 FFTPE Registers141726.4.1.4 DFTPE Registers141726.4.2 Detailed Descriptions141826.4.2.1 Buffer Descriptors (BD)141826.4.2.1.1 MAPLE BD Rings Configuration Parameter (MBDRCP)141826.4.2.1.2 MAPLE UCode Version Parameter (MUCVP)142026.4.2.1.3 MAPLE Timer Period Parameter (MP_TPP).142126.4.2.1.4 MAPLE TVPE BD Ring High Priority A <x> Parameter (MTVBRHPAxP)142226.4.2.1.5 MAPLE TVPE BD Ring High Priority B <x> Parameter (MTVBRHPBxP)142326.4.2.1.6 MAPLE TVPE BD Ring Low Priority A <x> Parameter (MTVBRLPAxP)142426.4.2.1.7 MAPLE TVPE BD Ring Low Priority B <x> Parameter (MTVBRLPBxP)142526.4.2.1.8 MAPLE FFTPE BD Ring High Priority A <x> Parameter (MFFBRHPAxP)142726.4.2.1.9 MAPLE FFTPE BD Ring High Priority B <x> Parameter (MFFBRHPBxP)142826.4.2.1.10 MAPLE FFTPE BD Ring Low Priority A <x> Parameter (MFFBRLPAxP)142926.4.2.1.11 MAPLE FFTPE BD Ring Low Priority B <x> Parameter (MFFBRLPBxP)143026.4.2.1.12 MAPLE DFTPE BD Ring High Priority A <x> Parameter (MDFBRHPAxP)143126.4.2.1.13 MAPLE DFTPE BD Ring High Priority B <x> Parameter (MDFBRHPBxP)143326.4.2.1.14 MAPLE DFTPE BD Ring Low Priority A <x> Parameter (MDFBRLPAxP)143426.4.2.1.15 MAPLE DFTPE BD Ring Low Priority B <x> Parameter (MDFBRLPBxP)143526.4.2.1.16 MAPLE CRCPE BD Ring High Priority A <x> Parameter (MCRCBRHPAxP)143626.4.2.1.17 MAPLE CRCPE BD Ring High Priority B <x> Parameter (MCRCBRHPBxP)143726.4.2.1.18 MAPLE CRCPE BD Ring Low Priority A <x> Parameter (MCRCBRLPAxP)143926.4.2.1.19 MAPLE CRCPE BD Ring Low Priority B <x> Parameter (MCRCBRLPBxP)144026.4.2.2 MAPLE Operating Parameters144126.4.2.2.1 MAPLE- Turbo Stop Criteria Configuration Parameter(MTSCCP)144126.4.2.2.2 MAPLE Turbo Viterbi Puncturing Vector x High Configuration Parameter (MTVPVxHCP)144226.4.2.2.3 MAPLE Turbo Viterbi Puncturing Vector x Low Configuration Parameter (MTVPVxLCP)144326.4.2.2.4 MAPLE Turbo Viterbi Puncturing Period Configuration y Parameter (MTVPPCyP)144426.4.2.2.5 MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 0 Parameter (MTVPVSxC0P)144526.4.2.2.6 MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 1 Parameter (MTVPVSxC1P)144626.4.2.3 Profiling Parameters144726.4.2.3.1 MAPLE-B Turbo Total Performance Parameter (MTTPP)144726.4.2.3.2 MAPLE-B Viterbi Total Performance Parameter (MVTPP)144726.4.2.3.3 MAPLE-B Total BLER Parameter (MTBP)144826.4.2.3.4 MAPLE-B TVPE BDs Counter Parameter (MTBDCP)144926.4.2.3.5 MAPLE-B FFT Total Performance Parameter (MFTPP)144926.4.2.3.6 MAPLE-B FFTPE BDs Counter Parameter (MFBDCP)145026.4.2.3.7 MAPLE-B DFT Total Performance Parameter (MDTPP)145126.4.2.3.8 MAPLE-B DFTPE BDs Counter Parameter (MDBDCP)145126.4.2.3.9 MAPLE-B Profiling Enable Parameter (MPEP)145226.4.2.4 Serial RapidIO Doorbell Support Attributes Parameters145326.4.2.4.1 Serial RapidIO Outbound RapidIO Doorbell Base Address Parameter (SORDP0BAP)145326.4.2.4.2 Hardware Semaphore Base Address Parameter (HSP0BAP)145426.4.2.4.3 MAPLE-B Doorbell Hardware Semaphore ID Configuration Parameter (MDHSIDCP)145526.4.2.4.4 MAPLE-B Doorbell General Configuration Parameter (MDGCP)145626.4.3 PSIF Registers145726.4.3.1 PSIF Command Register (PCR)145726.4.3.2 PSIF PIC Event Register (PSPICER)145826.4.3.3 PSIF PIC Edge/Level Register(PSPICELR)145926.4.3.4 PSIF PIC Mask Register(PSPICMR)146026.4.3.5 PSIF PIC Interrupts Assertion Clocks Register (PSPICIACR)146126.4.4 Processing Engine Registers146226.4.4.1 TVPE Registers146226.4.4.1.1 TVPE Configuration 0 Register (TVPEC0R)146226.4.4.1.2 TVPE Symbol Identification 0 Configuration Register (TVSI0CR)146326.4.4.1.3 TVPE Symbol Identification 1 Configuration Register (TVSI1CR)146626.4.4.1.4 TVPE Turbo Tail Symbol Identification x Configuration Register (TVTTSIxCR)146726.4.4.1.5 TVPE Aposteriori Quality Configuration Register (TVAQCR)146926.4.4.1.6 TVPE Viterbi Polynomial Vector Generation 0 Configuration Register (TVVPVG0CR)147026.4.4.1.7 TVPE Viterbi Polynomial Vector Generation 1 Configuration Register (TVVPVG1CR)147126.4.4.1.8 TVPE Decoder Status Register (TVPESR)147226.4.4.2 FFTPE Registers147326.4.4.2.1 FFTPE Data Size Register 0 (FFTPEDSR0)147326.4.4.2.2 FFTPE Data Size Register 1 (FFTPEDSR1)147426.4.4.2.3 FFTPE Data Size Register 2 (FFTPEDSR2)147526.4.4.2.4 FFTPE Status Register (FFTPESTR)147626.4.4.2.5 FFTPE Scaling Status Register (FFTPESCLSTR)147726.4.4.2.6 FFTPE Saturation Status Register 0 (FFTPESSTR0)147826.4.4.2.7 FFTPE Saturation Status Register 1 (FFTPESSTR1)147926.4.4.2.8 FFTPE Saturation Status Register 2 (FFTPESSTR2)148026.4.4.2.9 FFTPE Saturation Status Register 3 (FFTPESSTR3)148126.4.4.3 DFTPE Registers148226.4.4.3.1 DFTPE Data Size Register 0 (DFTPEDSR0)148226.4.4.3.2 DFTPE Data Size Register 1 (DFTPEDSR1)148326.4.4.3.3 DFTPE Data Size Register 2 (DFTPEDSR2)148426.4.4.4 DFTPE Status Registers148526.4.4.4.1 DFTPE Status Register (DFTPESTR)148526.4.4.4.2 DFTPE Scaling Status Register (DFTPESCLSTR)148626.4.4.4.3 DFTPE Saturation Status Register 0 (DFTPESSTR0)148726.4.4.4.4 DFTPE Saturation Status Register 1 (DFTPESSTR1)148826.4.4.4.5 DFTPE Saturation Status Register 2 (DFTPESSTR2)148926.4.4.4.6 DFTPE Saturation Status Register 3(DFTPESSTR3)1490Tamanho: 20 MBPáginas: 1490Language: EnglishAbrir o manual