Freescale Semiconductor MSC8156 Evaluation Module MSC8156EVM MSC8156EVM Manual Do Utilizador
Códigos do produto
MSC8156EVM
MSC8156
Reference Manual, Rev. 2
15-66
Freescale
Semiconductor
High Speed Serial Interface (HSSI) Subsystem
EICE
12–8
0
Lane E Receiver Idle Detection Control
The field is broken into two subfields. The
highest order 3 bits set the general
detection level. The lowest order 2 bits
control exit from idle for the PCI Express
interface.
Recommended setting per protocol:
• PCI Express: 10000.
• SGMII: 00100.
• Serial RapidIO: 00000.
The field is broken into two subfields. The
highest order 3 bits set the general
detection level. The lowest order 2 bits
control exit from idle for the PCI Express
interface.
Recommended setting per protocol:
• PCI Express: 10000.
• SGMII: 00100.
• Serial RapidIO: 00000.
EICE[12–10]:
000
000
Loss of signal detect function disabled.
001
Default SGMII levels (Low = 30 mV, High =
100 mV)
100 mV)
010
Intermediate level (Low =38 mV, High = 120
mV)
mV)
011
Intermediate level (Low = 50 mV, High 150
mV)
mV)
100
Default PCI Express levels (Low = 65 mV,
High = 175 mV)
High = 175 mV)
101
Low = 75 mV, High = 200 mV
110
Intermediate level (Low = 88 mV, High = 225
mV)
mV)
111
Intermediate level (Low = 100 mV, High =
250 mV)
250 mV)
EICE9–8]:
00
00
Exit from Idle ~88 UI and Unexpected Idle
Detect ~1 µs (application mode).
Detect ~1 µs (application mode).
01
Exit from Idle ~88 UI and Unexpected Idle
Detect ~10 µs
Detect ~10 µs
10
Exit from Idle ~88 UI and Unexpected Idle
Detect ~1 µs
Detect ~1 µs
11
Bypass
—
7–5
0
Reserved. Write to zero for future compatibility.
EICF
4–0
0
Lane F Receiver Idle Detection Control
The field is broken into two subfields. The
highest order 3 bits set the general
detection level. The lowest order 2 bits
control exit from idle for the PCI Express
interface.
Recommended setting per protocol:
• PCI Express: 10000.
• SGMII: 00100.
• Serial RapidIO: 00000.
The field is broken into two subfields. The
highest order 3 bits set the general
detection level. The lowest order 2 bits
control exit from idle for the PCI Express
interface.
Recommended setting per protocol:
• PCI Express: 10000.
• SGMII: 00100.
• Serial RapidIO: 00000.
EICF[4–2]:
000
000
Loss of signal detect function disabled.
001
Default SGMII levels (Low = 30 mV, High =
100 mV)
100 mV)
010
Intermediate level (Low =38 mV, High = 120
mV)
mV)
011
Intermediate level (Low = 50 mV, High 150
mV)
mV)
100
Default PCI Express levels (Low = 65 mV,
High = 175 mV)
High = 175 mV)
101
Low = 75 mV, High = 200 mV
110
Intermediate level (Low = 88 mV, High = 225
mV)
mV)
111
Intermediate level (Low = 100 mV, High =
250 mV)
250 mV)
EICF[1–0]:
00
00
Exit from Idle ~88 UI and Unexpected Idle
Detect ~1 µs (application mode).
Detect ~1 µs (application mode).
01
Exit from Idle ~88 UI and Unexpected Idle
Detect ~10 µs
Detect ~10 µs
10
Exit from Idle ~88 UI and Unexpected Idle
Detect ~1 µs
Detect ~1 µs
11
Bypass
Table 15-35. SRDSnCR4 Field Descriptions (Continued)
Bits
Reset
Description