Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Ficha De Dados
Códigos do produto
ATSAMD21-XPRO
458
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
25.8.7 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x18
Reset:
0x00
Property:
z
Bit 7– ERROR: Error
This flag is cleared by writing a one to it.
This flag is cleared by writing a one to it.
This bit is set when any error is detected. Errors that will set this flag have corresponding status flags in the
STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.
STATUS register. Errors that will set this flag are COLL, ISF, BUFOVF, FERR, and PERR.
Writing a zero to
this bit has no effect.
Writing a one to this bit will clear the flag.
Writing a one to this bit will clear the flag.
z
Bits 6 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 5 – RXBRK: Receive Break
This flag is cleared by writing a one to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
This flag is cleared by writing a one to it.
This flag is set when auto-baud is enabled (CTRLA.FORM) and a break character is received.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
z
Bit 4 – CTSIC: Clear to Send Input Change
This flag is cleared by writing a one to it.
This flag is set when a change is detected on the CTS pin.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
This flag is cleared by writing a one to it.
This flag is set when a change is detected on the CTS pin.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the flag.
z
Bit 3 – RXS: Receive Start
This flag is cleared by writing a one to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is one).
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start interrupt flag.
This flag is cleared by writing a one to it.
This flag is set when a start condition is detected on the RxD line and start-of-frame detection is enabled
(CTRLB.SFDE is one).
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Receive Start interrupt flag.
z
Bit 2 – RXC: Receive Complete
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This flag is cleared by reading the Data register (DATA) or by disabling the receiver.
This flag is set when there are unread data in DATA.
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
z
Bit 1 – TXC: Transmit Complete
This flag is cleared by writing a one to it or by writing new data to DATA.
This flag is cleared by writing a one to it or by writing new data to DATA.
Bit
7
6
5
4
3
2
1
0
ERROR
RXBRK
CTSIC
RXS
RXC
TXC
DRE
Access
R/W
R
R/W
R/W
R/W
R
R/W
R
Reset
0
0
0
0
0
0
0
0