Manuais de utilizador para Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO

Atmel

Códigos do produto

ATSAMD21-XPRO

Ficha De Dados (English)Ficha De Dados (English)

Ficha De Dados (ATSAMD21-XPRO)

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Ficha De Dados (ATSAMD21-XPRO)

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700 KB
Páginas:

17
Language:

English

Ficha De Dados (ATSAMD21-XPRO)

índice analítico

Description
1
Features
2
1. Configuration Summary
3
2. Ordering Information
5
- 2.1 SAM D21E
  5
- 2.2 SAM D21G
  6
- 2.3 SAM D21J
  6
3. Block Diagram
8
4. Pinout
9
- 4.1 SAM D21J
  9
- 4.2 SAM D21G
  10
- 4.3 SAM D21E
  11
5. Signal Descriptions List
12
6. I/O Multiplexing and Considerations
14
- 6.1 Multiplexed Signals
  14
- 6.2 Other Functions
  17
  - 6.2.1 Oscillator Pinout
    17
  - 6.2.2 Serial Wire Debug Interface Pinout
    17
7. Power Supply and Start-Up Considerations
18
- 7.1 Power Domain Overview
  18
- 7.2 Power Supply Considerations
  18
- 7.3 Power-Up
  20
- 7.4 Power-On Reset and Brown-Out Detector
  20
8. Product Mapping
21
9. Memories
22
- 9.1 Embedded Memories
  22
- 9.2 Physical Memory Map
  22
- 9.3 NVM Calibration and Auxiliary Space
  23
10. Processor And Architecture
26
- 10.1 Cortex M0+ Processor
  26
- 10.2 Nested Vector Interrupt Controller
  27
  - 10.2.1 Overview
    27
  - 10.2.2 Interrupt Line Mapping
    27
- 10.3 Micro Trace Buffer
  29
  - 10.3.1 Features
    29
  - 10.3.2 Overview
    29
- 10.4 High-Speed Bus System
  29
- 10.5 AHB-APB Bridge
  32
- 10.6 PAC – Peripheral Access Controller
  33
  - 10.6.1 Overview
    33
  - 10.6.2 Register Description
    34
11. Peripherals Configuration Summary
40
12. DSU – Device Service Unit
42
- 12.1 Overview
  42
- 12.2 Features
  42
- 12.3 Block Diagram
  42
- 12.4 Signal Description
  43
- 12.5 Product Dependencies
  43
  - 12.5.1 I/O Lines
    43
  - 12.5.2 Power Management
    43
  - 12.5.3 Clocks
    43
  - 12.5.4 DMA
    43
  - 12.5.5 Interrupts
    43
  - 12.5.6 Events
    43
  - 12.5.7 Register Access Protection
    43
  - 12.5.8 Analog Connections
    44
- 12.6 Debug Operation
  44
- 12.7 Chip-Erase
  45
- 12.8 Programming
  45
- 12.9 Intellectual Property Protection
  46
- 12.10 Device Identification
  47
  - 12.10.1 CoreSight Identification
    47
  - 12.10.2 DSU Chip Identification Method:
    48
- 12.11 Functional Description
  48
- 12.12 Register Summary
  53
- 12.13 Register Description
  56
13. Clock System
78
- 13.1 Clock Distribution
  78
- 13.2 Synchronous and Asynchronous Clocks
  79
- 13.3 Register Synchronization
  79
- 13.4 Enabling a Peripheral
  82
- 13.5 On-demand, Clock Requests
  82
- 13.6 Power Consumption vs Speed
  83
- 13.7 Clocks after Reset
  83
14. GCLK – Generic Clock Controller
84
- 14.1 Overview
  84
- 14.2 Features
  84
- 14.3 Block Diagram
  84
- 14.4 Signal Description
  85
- 14.5 Product Dependencies
  85
  - 14.5.1 I/O Lines
    85
  - 14.5.2 Power Management
    85
  - 14.5.3 Clocks
    85
  - 14.5.4 DMA
    86
  - 14.5.5 Interrupts
    86
  - 14.5.6 Events
    86
  - 14.5.7 Debug Operation
    86
  - 14.5.8 Register Access Protection
    86
  - 14.5.9 Analog Connections
    86
- 14.6 Functional Description
  86
- 14.7 Register Summary
  91
- 14.8 Register Description
  92
15. PM – Power Manager
106
- 15.1 Overview
  106
- 15.2 Features
  106
- 15.3 Block Diagram
  107
- 15.4 Signal Description
  107
- 15.5 Product Dependencies
  107
  - 15.5.1 I/O Lines
    107
  - 15.5.2 Power Management
    107
  - 15.5.3 Clocks
    108
    - 15.5.3.1 Main Clock
      108
    - 15.5.3.2 CPU Clock
      108
    - 15.5.3.3 AHB Clock
      108
    - 15.5.3.4 APBx Clocks
      108
  - 15.5.4 DMA
    108
  - 15.5.5 Interrupts
    108
  - 15.5.6 Events
    108
  - 15.5.7 Debug Operation
    108
  - 15.5.8 Register Access Protection
    108
  - 15.5.9 Analog Connections
    109
- 15.6 Functional Description
  109
  - 15.6.1 Principle of Operation
    109
  - 15.6.2 Basic Operation
    109
  - 15.6.3 SleepWalking
    115
  - 15.6.4 DMA Operation
    115
  - 15.6.5 Interrupts
    115
  - 15.6.6 Events
    115
  - 15.6.7 Sleep Mode Operation
    115
- 15.7 Register Summary
  116
- 15.8 Register Description
  117
  - 15.8.1 Control
    118
  - 15.8.2 Sleep Mode
    119
  - 15.8.3 CPU Clock Select
    120
  - 15.8.4 APBA Clock Select
    121
  - 15.8.5 APBB Clock Select
    122
  - 15.8.6 APBC Clock Select
    123
  - 15.8.7 AHB Mask
    124
  - 15.8.8 APBA Mask
    126
  - 15.8.9 APBB Mask
    128
  - 15.8.10 APBC Mask
    130
  - 15.8.11 Interrupt Enable Clear
    133
  - 15.8.12 Interrupt Enable Set
    134
  - 15.8.13 Interrupt Flag Status and Clear
    135
  - 15.8.14 Reset Cause
    136
16. SYSCTRL – System Controller
138
- 16.1 Overview
  138
- 16.2 Features
  138
- 16.3 Block Diagram
  139
- 16.4 Signal Description
  140
- 16.5 Product Dependencies
  140
  - 16.5.1 I/O Lines
    140
  - 16.5.2 Power Management
    140
  - 16.5.3 Clocks
    140
  - 16.5.4 Interrupts
    140
  - 16.5.5 Debug Operation
    140
  - 16.5.6 Register Access Protection
    141
  - 16.5.7 Analog Connections
    141
- 16.6 Functional Description
  141
- 16.7 Register Summary
  155
- 16.8 Register Description
  157
17. WDT – Watchdog Timer
200
- 17.1 Overview
  200
- 17.2 Features
  200
- 17.3 Block Diagram
  200
- 17.4 Signal Description
  201
- 17.5 Product Dependencies
  201
  - 17.5.1 I/O Lines
    201
  - 17.5.2 Power Management
    201
  - 17.5.3 Clocks
    201
  - 17.5.4 DMA
    201
  - 17.5.5 Interrupts
    201
  - 17.5.6 Events
    201
  - 17.5.7 Debug Operation
    201
  - 17.5.8 Register Access Protection
    202
  - 17.5.9 Analog Connections
    202
- 17.6 Functional Description
  202
  - 17.6.1 Principle of Operation
    202
  - 17.6.2 Basic Operation
    202
    - 17.6.2.1 Initialization
      202
    - 17.6.2.2 Configurable Reset Values
      203
    - 17.6.2.3 Enabling and Disabling
      203
    - 17.6.2.4 Normal Mode
      203
    - 17.6.2.5 Window Mode
      204
  - 17.6.3 Additional Features
    205
    - 17.6.3.1 Always-On Mode
      205
  - 17.6.4 Interrupts
    205
  - 17.6.5 Synchronization
    206
- 17.7 Register Summary
  207
- 17.8 Register Description
  208
  - 17.8.1 Control
    209
  - 17.8.2 Configuration
    210
  - 17.8.3 Early Warning Interrupt Control
    212
  - 17.8.4 Interrupt Enable Clear
    213
  - 17.8.5 Interrupt Enable Set
    214
  - 17.8.6 Interrupt Flag Status and Clear
    215
  - 17.8.7 Status
    216
  - 17.8.8 Clear
    217
18. RTC – Real-Time Counter
218
- 18.1 Overview
  218
- 18.2 Features
  218
- 18.3 Block Diagram
  218
- 18.4 Signal Description
  219
- 18.5 Product Dependencies
  219
  - 18.5.1 I/O Lines
    219
  - 18.5.2 Power Management
    219
  - 18.5.3 Clocks
    220
  - 18.5.4 DMA
    220
  - 18.5.5 Interrupts
    220
  - 18.5.6 Events
    220
  - 18.5.7 Debug Operation
    220
  - 18.5.8 Register Access Protection
    220
  - 18.5.9 Analog Connections
    220
- 18.6 Functional Description
  221
  - 18.6.1 Principle of Operation
    221
  - 18.6.2 Basic Operation
    221
    - 18.6.2.1 Initialization
      221
    - 18.6.2.2 Enabling, Disabling and Resetting
      221
  - 18.6.3 Operating Modes
    222
  - 18.6.4 Additional Features
    223
    - 18.6.4.1 Periodic Events
      223
    - 18.6.4.2 Frequency Correction
      223
  - 18.6.5 DMA Operation
    224
  - 18.6.6 Interrupts
    224
  - 18.6.7 Events
    224
  - 18.6.8 Sleep Mode Operation
    224
  - 18.6.9 Synchronization
    225
- 18.7 Register Summary
  226
- 18.8 Register Description
  229
19. DMAC – Direct Memory Access Controller
261
- 19.1 Overview
  261
- 19.2 Features
  261
- 19.3 Block Diagram
  262
- 19.4 Signal Description
  262
- 19.5 Product Dependencies
  262
  - 19.5.1 I/O Lines
    263
  - 19.5.2 Power Management
    263
  - 19.5.3 Clocks
    263
  - 19.5.4 DMA
    263
  - 19.5.5 Interrupts
    263
  - 19.5.6 Events
    263
  - 19.5.7 Debug Operation
    263
  - 19.5.8 Register Access Protection
    263
  - 19.5.9 Analog Connections
    263
- 19.6 Functional Description
  264
  - 19.6.1 Principle of Operation
    264
    - 19.6.1.1 DMA
      264
    - 19.6.1.2 CRC
      264
  - 19.6.2 Basic Operation
    265
    - 19.6.2.1 Initialization
      265
    - 19.6.2.2 Enabling, Disabling and Resetting
      266
    - 19.6.2.3 Transfer Descriptors
      266
    - 19.6.2.4 Arbitration
      268
    - 19.6.2.5 Data Transmission
      269
    - 19.6.2.6 Transfer Triggers and Actions
      270
    - 19.6.2.7 Addressing
      271
    - 19.6.2.8 Error Handling
      273
  - 19.6.3 Additional Features
    273
  - 19.6.4 DMA Operation
    280
  - 19.6.5 Interrupts
    280
  - 19.6.6 Events
    280
  - 19.6.7 Sleep Mode Operation
    281
  - 19.6.8 Synchronization
    281
- 19.7 Register Summary
  282
- 19.8 Register Description
  285
  - 19.8.1 DMAC Registers
    286
  - 19.8.2 DMAC SRAM Registers
    318
20. EIC – External Interrupt Controller
325
- 20.1 Overview
  325
- 20.2 Features
  325
- 20.3 Block Diagram
  325
- 20.4 Signal Description
  326
- 20.5 Product Dependencies
  326
  - 20.5.1 I/O Lines
    326
  - 20.5.2 Power Management
    326
  - 20.5.3 Clocks
    326
  - 20.5.4 DMA
    326
  - 20.5.5 Interrupts
    326
  - 20.5.6 Events
    326
  - 20.5.7 Debug Operation
    327
  - 20.5.8 Register Access Protection
    327
  - 20.5.9 Analog Connections
    327
- 20.6 Functional Description
  327
  - 20.6.1 Principle of Operation
    327
  - 20.6.2 Basic Operation
    327
    - 20.6.2.1 Initialization
      327
    - 20.6.2.2 Enabling, Disabling and Resetting
      327
  - 20.6.3 External Pin Processing
    327
  - 20.6.4 Additional Features
    329
  - 20.6.5 DMA Operation
    329
  - 20.6.6 Interrupts
    329
  - 20.6.7 Events
    329
  - 20.6.8 Sleep Mode Operation
    330
  - 20.6.9 Synchronization
    330
- 20.7 Register Summary
  331
- 20.8 Register Description
  332
  - 20.8.1 Control
    333
  - 20.8.2 Status
    334
  - 20.8.3 Non-Maskable Interrupt Control
    335
  - 20.8.4 Non-Maskable Interrupt Flag Status and Clear
    336
  - 20.8.5 Event Control
    337
  - 20.8.6 Interrupt Enable Clear
    338
  - 20.8.7 Interrupt Enable Set
    339
  - 20.8.8 Interrupt Flag Status and Clear
    340
  - 20.8.9 Wake-Up Enable
    341
  - 20.8.10 Configuration n
    342
21. NVMCTRL – Non-Volatile Memory Controller
344
- 21.1 Overview
  344
- 21.2 Features
  344
- 21.3 Block Diagram
  344
- 21.4 Signal Description
  344
- 21.5 Product Dependencies
  345
  - 21.5.1 Power Management
    345
  - 21.5.2 Clocks
    345
  - 21.5.3 Interrupts
    345
  - 21.5.4 Debug Operation
    345
  - 21.5.5 Register Access Protection
    345
  - 21.5.6 Analog Connections
    345
- 21.6 Functional Description
  345
  - 21.6.1 Principle of Operation
    345
  - 21.6.2 Basic Operations
    346
    - 21.6.2.1 Initialization
      346
    - 21.6.2.2 Enabling, Disabling and Resetting
      346
  - 21.6.3 Memory Organization
    346
  - 21.6.4 Region Lock Bits
    347
  - 21.6.5 Command and Data Interface
    347
    - 21.6.5.1 NVM Read
      348
    - 21.6.5.2 NVM Write
      348
    - 21.6.5.3 Page Buffer Clear
      349
    - 21.6.5.4 Erase Row
      349
    - 21.6.5.5 Lock and Unlock Region
      349
    - 21.6.5.6 Set and Clear Power Reduction Mode
      349
  - 21.6.6 NVM User Configuration
    349
  - 21.6.7 Security Bit
    350
  - 21.6.8 Cache
    350
- 21.7 Register Summary
  351
- 21.8 Register Description
  352
  - 21.8.1 Control A
    353
  - 21.8.2 Control B
    355
  - 21.8.3 NVM Parameter
    358
  - 21.8.4 Interrupt Enable Clear
    360
  - 21.8.5 Interrupt Enable Set
    361
  - 21.8.6 Interrupt Flag Status and Clear
    362
  - 21.8.7 Status
    363
  - 21.8.8 Address
    365
  - 21.8.9 Lock Section
    366
22. PORT
367
- 22.1 Overview
  367
- 22.2 Features
  367
- 22.3 Block Diagram
  368
- 22.4 Signal Description
  368
- 22.5 Product Dependencies
  368
  - 22.5.1 I/O Lines
    368
  - 22.5.2 Power Management
    369
  - 22.5.3 Clocks
    369
  - 22.5.4 DMA
    369
  - 22.5.5 Interrupts
    369
  - 22.5.6 Events
    369
  - 22.5.7 Debug Operation
    369
  - 22.5.8 Register Access Protection
    369
  - 22.5.9 Analog Connections
    369
  - 22.5.10 CPU Local Bus
    369
- 22.6 Functional Description
  370
- 22.7 Register Summary
  375
- 22.8 Register Description
  377
  - 22.8.1 Data Direction
    378
  - 22.8.2 Data Direction Clear
    379
  - 22.8.3 Data Direction Set
    380
  - 22.8.4 Data Direction Toggle
    381
  - 22.8.5 Data Output Value
    382
  - 22.8.6 Data Output Value Clear
    383
  - 22.8.7 Data Output Value Set
    384
  - 22.8.8 Data Output Value Toggle
    385
  - 22.8.9 Data Input Value
    386
  - 22.8.10 Control
    387
  - 22.8.11 Write Configuration
    388
  - 22.8.12 Peripheral Multiplexing n
    391
  - 22.8.13 Pin Configuration n
    393
23. EVSYS – Event System
394
- 23.1 Overview
  394
- 23.2 Features
  394
- 23.3 Block Diagram
  395
- 23.4 Signal Description
  395
- 23.5 Product Dependencies
  395
  - 23.5.1 I/O Lines
    395
  - 23.5.2 Power Management
    395
  - 23.5.3 Clocks
    395
  - 23.5.4 DMA
    395
  - 23.5.5 Interrupts
    396
  - 23.5.6 Events
    396
  - 23.5.7 Debug Operation
    396
  - 23.5.8 Register Access Protection
    396
  - 23.5.9 Analog Connections
    396
- 23.6 Functional Description
  396
  - 23.6.1 Principle of Operation
    396
  - 23.6.2 Basic Operation
    396
    - 23.6.2.1 Initialization
      396
    - 23.6.2.2 Enabling, Disabling and Resetting
      396
    - 23.6.2.3 Channel Path
      397
    - 23.6.2.4 User Multiplexer Setup
      398
    - 23.6.2.5 Channel Setup
      398
    - 23.6.2.6 Edge Detection
      399
    - 23.6.2.7 Channel Status
      399
    - 23.6.2.8 Software Event
      399
  - 23.6.3 Interrupts
    399
    - 23.6.3.1 The Overrun Channel x Interrupt
      400
    - 23.6.3.2 The Event Detected Channel x Interrupt
      400
  - 23.6.4 Sleep Mode Operation
    400
- 23.7 Register Summary
  401
- 23.8 Register Description
  402
  - 23.8.1 Control
    403
  - 23.8.2 Channel
    404
  - 23.8.3 User Multiplexer
    409
  - 23.8.4 Channel Status
    411
  - 23.8.5 Interrupt Enable Clear
    413
  - 23.8.6 Interrupt Enable Set
    415
  - 23.8.7 Interrupt Flag Status and Clear
    417
24. SERCOM – Serial Communication Interface
420
- 24.1 Overview
  420
- 24.2 Features
  420
- 24.3 Block Diagram
  420
- 24.4 Signal Description
  420
- 24.5 Product Dependencies
  421
  - 24.5.1 I/O Lines
    421
  - 24.5.2 Power Management
    421
  - 24.5.3 Clocks
    421
  - 24.5.4 DMA
    421
  - 24.5.5 Interrupts
    421
  - 24.5.6 Events
    421
  - 24.5.7 Debug Operation
    421
  - 24.5.8 Register Access Protection
    422
  - 24.5.9 Analog Connections
    422
- 24.6 Functional Description
  422
  - 24.6.1 Principle of Operation
    422
  - 24.6.2 Basic Operation
    423
  - 24.6.3 Additional Features
    426
    - 24.6.3.1 Address Match and Mask
      426
  - 24.6.4 DMA Operation
    426
  - 24.6.5 Interrupts
    427
  - 24.6.6 Events
    427
  - 24.6.7 Sleep Mode Operation
    427
  - 24.6.8 Synchronization
    427
25. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
428
- 25.1 Overview
  428
- 25.2 Features
  428
- 25.3 Block Diagram
  429
- 25.4 Signal Description
  429
- 25.5 Product Dependencies
  429
  - 25.5.1 I/O Lines
    429
  - 25.5.2 Power Management
    430
  - 25.5.3 Clocks
    430
  - 25.5.4 DMA
    430
  - 25.5.5 Interrupts
    430
  - 25.5.6 Events
    430
  - 25.5.7 Debug Operation
    430
  - 25.5.8 Register Access Protection
    430
  - 25.5.9 Analog Connections
    431
- 25.6 Functional Description
  431
  - 25.6.1 Principle of Operation
    431
  - 25.6.2 Basic Operation
    431
  - 25.6.3 Additional Features
    435
  - 25.6.4 DMA, Interrupts and Events
    439
    - 25.6.4.1 DMA Operation
      439
    - 25.6.4.2 Interrupts
      440
    - 25.6.4.3 Events
      440
  - 25.6.5 Sleep Mode Operation
    440
  - 25.6.6 Synchronization
    440
- 25.7 Register Summary
  442
- 25.8 Register Description
  444
  - 25.8.1 Control A
    445
  - 25.8.2 Control B
    449
  - 25.8.3 Baud
    452
  - 25.8.4 Receive Pulse Length Register
    453
  - 25.8.5 Interrupt Enable Clear
    454
  - 25.8.6 Interrupt Enable Set
    456
  - 25.8.7 Interrupt Flag Status and Clear
    458
  - 25.8.8 Status
    460
  - 25.8.9 Synchronization Busy
    462
  - 25.8.10 Data
    464
  - 25.8.11 Debug Control
    465
26. SERCOM SPI – SERCOM Serial Peripheral Interface
466
- 26.1 Overview
  466
- 26.2 Features
  466
- 26.3 Block Diagram
  466
- 26.4 Signal Description
  466
- 26.5 Product Dependencies
  467
  - 26.5.1 I/O Lines
    467
  - 26.5.2 Power Management
    467
  - 26.5.3 Clocks
    467
  - 26.5.4 DMA
    467
  - 26.5.5 Interrupts
    467
  - 26.5.6 Events
    468
  - 26.5.7 Debug Operation
    468
  - 26.5.8 Register Access Protection
    468
  - 26.5.9 Analog Connections
    468
- 26.6 Functional Description
  468
  - 26.6.1 Principle of Operation
    468
  - 26.6.2 Basic Operation
    469
    - 26.6.2.1 Initialization
      469
    - 26.6.2.2 Enabling, Disabling and Resetting
      469
    - 26.6.2.3 Clock Generation
      469
    - 26.6.2.4 Data Register
      470
    - 26.6.2.5 SPI Transfer Modes
      470
    - 26.6.2.6 Transferring Data
      471
    - 26.6.2.7 Receiver Error Bit
      472
  - 26.6.3 Additional Features
    472
  - 26.6.4 DMA, Interrupts and Events
    475
    - 26.6.4.1 DMA Operation
      475
    - 26.6.4.2 Interrupts
      475
    - 26.6.4.3 Events
      475
  - 26.6.5 Sleep Mode Operation
    476
  - 26.6.6 Synchronization
    476
- 26.7 Register Summary
  477
- 26.8 Register Description
  479
  - 26.8.1 Control A
    480
  - 26.8.2 Control B
    484
  - 26.8.3 Baud Rate
    486
  - 26.8.4 Interrupt Enable Clear
    487
  - 26.8.5 Interrupt Enable Set
    489
  - 26.8.6 Interrupt Flag Status and Clear
    491
  - 26.8.7 Status
    493
  - 26.8.8 Synchronization Busy
    494
  - 26.8.9 Address
    496
  - 26.8.10 Data
    497
  - 26.8.11 Debug Control
    498
27. SERCOM I2C – SERCOM Inter-Integrated Circuit
499
- 27.1 Overview
  499
- 27.2 Features
  499
- 27.3 Block Diagram
  499
- 27.4 Signal Description
  500
- 27.5 Product Dependencies
  500
  - 27.5.1 I/O Lines
    500
  - 27.5.2 Power Management
    500
  - 27.5.3 Clocks
    500
  - 27.5.4 DMA
    500
  - 27.5.5 Interrupts
    500
  - 27.5.6 Events
    501
  - 27.5.7 Debug Operation
    501
  - 27.5.8 Register Access Protection
    501
  - 27.5.9 Analog Connections
    501
- 27.6 Functional Description
  501
- 27.7 Register Summary
  519
- 27.8 Register Description
  524
  - 27.8.1 I2C Slave Register Description
    525
    - 27.8.1.1 Control A
      525
    - 27.8.1.2 Control B
      528
    - 27.8.1.3 Interrupt Enable Clear
      531
    - 27.8.1.4 Interrupt Enable Set
      532
    - 27.8.1.5 Interrupt Flag Status and Clear
      533
    - 27.8.1.6 Status
      534
    - 27.8.1.7 Synchronization Busy
      536
    - 27.8.1.8 Address
      537
    - 27.8.1.9 Data
      539
  - 27.8.2 I2C Master Register Description
    540
    - 27.8.2.1 Control A
      540
    - 27.8.2.2 Control B
      544
    - 27.8.2.3 Baud Rate
      546
    - 27.8.2.4 Interrupt Enable Clear
      548
    - 27.8.2.5 Interrupt Enable Set
      549
    - 27.8.2.6 Interrupt Flag Status and Clear
      550
    - 27.8.2.7 Status
      552
    - 27.8.2.8 Syncbusy
      555
    - 27.8.2.9 Address
      557
    - 27.8.2.10 Data
      560
    - 27.8.2.11 Debug Control
      561
28. I2S - Inter-IC Sound Controller
562
- 28.1 Overview
  562
- 28.2 Features
  562
- 28.3 Block Diagram
  563
- 28.4 Signal Description
  563
- 28.5 Product Dependencies
  564
  - 28.5.1 I/O lines
    564
  - 28.5.2 Power Management
    564
  - 28.5.3 Clocks
    564
  - 28.5.4 DMA
    564
  - 28.5.5 Interrupts
    564
  - 28.5.6 Events
    564
  - 28.5.7 Debug Operation
    565
  - 28.5.8 Register Access Protection
    565
  - 28.5.9 Analog Connections
    565
- 28.6 Functional Description
  566
- 28.7 I2S Application Examples
  577
- 28.8 Register Summary
  579
- 28.9 Register Description
  581
  - 28.9.1 Control A
    582
  - 28.9.2 Clock Unit n Control
    583
  - 28.9.3 Interrupt Enable Clear
    586
  - 28.9.4 Interrupt Enable Set
    588
  - 28.9.5 Interrupt Flag Status and Clear
    590
  - 28.9.6 Synchronization Busy
    592
  - 28.9.7 Serializer n Control
    593
  - 28.9.8 Data Holding m
    597
29. TC – Timer/Counter
598
- 29.1 Overview
  598
- 29.2 Features
  598
- 29.3 Block Diagram
  599
- 29.4 Signal Description
  600
- 29.5 Product Dependencies
  600
  - 29.5.1 I/O Lines
    600
  - 29.5.2 Power Management
    600
  - 29.5.3 Clocks
    600
  - 29.5.4 DMA
    600
  - 29.5.5 Interrupts
    600
  - 29.5.6 Events
    600
  - 29.5.7 Debug Operation
    600
  - 29.5.8 Register Access Protection
    601
  - 29.5.9 Analog Connections
    601
- 29.6 Functional Description
  601
  - 29.6.1 Principle of Operation
    601
  - 29.6.2 Basic Operation
    601
    - 29.6.2.1 Initialization
      601
    - 29.6.2.2 Enabling, Disabling and Resetting
      602
    - 29.6.2.3 Prescaler Selection
      602
    - 29.6.2.4 TC Mode
      603
    - 29.6.2.5 Counter Operations
      603
    - 29.6.2.6 Compare Operations
      604
    - 29.6.2.7 Capture Operations
      607
  - 29.6.3 Additional Features
    608
    - 29.6.3.1 One-Shot Operation
      608
  - 29.6.4 DMA, Interrupts and Events
    609
    - 29.6.4.1 DMA Operation
      609
    - 29.6.4.2 Interrupts
      610
    - 29.6.4.3 Events
      610
  - 29.6.5 Sleep Mode Operation
    610
  - 29.6.6 Synchronization
    610
- 29.7 Register Summary
  612
- 29.8 Register Description
  615
  - 29.8.1 Control A
    616
  - 29.8.2 Read Request
    619
  - 29.8.3 Control B Clear
    620
  - 29.8.4 Control B Set
    622
  - 29.8.5 Control C
    624
  - 29.8.6 Debug Control
    625
  - 29.8.7 Event Control
    626
  - 29.8.8 Interrupt Enable Clear
    628
  - 29.8.9 Interrupt Enable Set
    629
  - 29.8.10 Interrupt Flag Status and Clear
    630
  - 29.8.11 Status
    631
  - 29.8.12 Counter Value
    632
    - 29.8.12.1 8-Bit Mode
      632
    - 29.8.12.2 16-Bit Mode
      633
    - 29.8.12.3 32-Bit Mode
      634
  - 29.8.13 Period Value
    635
    - 29.8.13.1 8-Bit Mode
      635
  - 29.8.14 Compare/Capture
    636
    - 29.8.14.1 8-Bit Mode
      636
    - 29.8.14.2 16-Bit Mode
      637
    - 29.8.14.3 32-Bit Mode
      638
30. TCC – Timer/Counter for Control Applications
639
- 30.1 Overview
  639
- 30.2 Features
  639
- 30.3 Block Diagram
  640
- 30.4 Signal Description
  640
- 30.5 Product Dependencies
  641
  - 30.5.1 I/O Lines
    641
  - 30.5.2 Power Management
    641
  - 30.5.3 Clocks
    641
  - 30.5.4 DMA
    641
  - 30.5.5 Interrupts
    641
  - 30.5.6 Events
    641
  - 30.5.7 Debug Operation
    641
  - 30.5.8 Register Access Protection
    641
  - 30.5.9 Analog Connections
    642
- 30.6 Functional Description
  642
  - 30.6.1 Principle of Operation
    642
  - 30.6.2 Basic Operation
    644
  - 30.6.3 Additional Features
    656
    - 30.6.3.1 One-Shot Operation
      656
    - 30.6.3.2 Circular Buffer
      656
    - 30.6.3.3 Dithering Operation
      656
    - 30.6.3.4 Ramp Operations
      658
    - 30.6.3.5 Recoverable Faults
      659
    - 30.6.3.6 Non Recoverable Faults
      665
    - 30.6.3.7 Waveform Extension
      666
  - 30.6.4 DMA, Interrupts and Events
    669
    - 30.6.4.1 DMA Operation
      669
    - 30.6.4.2 Interrupts
      669
    - 30.6.4.3 Events
      670
  - 30.6.5 Sleep Mode Operation
    671
  - 30.6.6 Synchronization
    671
- 30.7 Register Summary
  672
- 30.8 Register Description
  675
  - 30.8.1 Control A
    676
  - 30.8.2 Control B Clear
    679
  - 30.8.3 Control B Set
    681
  - 30.8.4 Synchronization Busy
    683
  - 30.8.5 Recoverable Fault A Configuration
    685
  - 30.8.6 Recoverable Fault B Configuration
    688
  - 30.8.7 Waveform Extension Configuration
    691
  - 30.8.8 Driver Control
    693
  - 30.8.9 Debug Control
    695
  - 30.8.10 Event Control
    696
  - 30.8.11 Interrupt Enable Clear
    699
  - 30.8.12 Interrupt Enable Set
    702
  - 30.8.13 Interrupt Flag Status and Clear
    705
  - 30.8.14 Status
    707
  - 30.8.15 Count
    710
  - 30.8.16 Pattern
    713
  - 30.8.17 Waveform Control
    714
  - 30.8.18 Period
    717
  - 30.8.19 Compare and Capture
    720
  - 30.8.20 Pattern Buffer
    723
  - 30.8.21 Waveform Control Buffer
    724
  - 30.8.22 Period Buffer
    726
  - 30.8.23 Compare and Capture Buffer
    729
31. USB – Universal Serial Bus
732
- 31.1 Overview
  732
- 31.2 Features
  732
- 31.3 USB Block Diagram
  733
- 31.4 Signal Description
  733
- 31.5 Product Dependencies
  733
  - 31.5.1 I/O Lines
    733
  - 31.5.2 Power Management
    734
  - 31.5.3 Clocks
    734
  - 31.5.4 DMA
    734
  - 31.5.5 Interrupts
    734
  - 31.5.6 Events
    734
  - 31.5.7 Debug Operation
    734
  - 31.5.8 Register Access Protection
    734
  - 31.5.9 Analog Connections
    735
  - 31.5.10 Calibration
    735
- 31.6 Functional Description
  736
- 31.7 Register Summary
  752
  - 31.7.1 Common Device Host Summary
    752
  - 31.7.2 Device Summary
    752
  - 31.7.3 Host Summary
    756
- 31.8 Register Description
  760
32. ADC – Analog-to-Digital Converter
832
- 32.1 Overview
  832
- 32.2 Features
  832
- 32.3 Block Diagram
  833
- 32.4 Signal Description
  833
- 32.5 Product Dependencies
  834
  - 32.5.1 I/O Lines
    834
  - 32.5.2 Power Management
    834
  - 32.5.3 Clocks
    834
  - 32.5.4 DMA
    834
  - 32.5.5 Interrupts
    834
  - 32.5.6 Events
    834
  - 32.5.7 Debug Operation
    834
  - 32.5.8 Register Access Protection
    834
  - 32.5.9 Analog Connections
    834
  - 32.5.10 Calibration
    835
- 32.6 Functional Description
  835
  - 32.6.1 Principle of Operation
    835
  - 32.6.2 Basic Operation
    835
  - 32.6.3 Prescaler
    836
  - 32.6.4 ADC Resolution
    836
  - 32.6.5 Differential and Single-Ended Conversions
    837
    - 32.6.5.1 Conversion Timing
      837
  - 32.6.6 Accumulation
    839
  - 32.6.7 Averaging
    839
  - 32.6.8 Oversampling and Decimation
    840
  - 32.6.9 Window Monitor
    840
  - 32.6.10 Offset and Gain Correction
    841
  - 32.6.11 DMA, Interrupts and Events
    842
    - 32.6.11.1 DMA Operation
      842
    - 32.6.11.2 Interrupts
      842
    - 32.6.11.3 Events
      842
  - 32.6.12 Sleep Mode Operation
    843
  - 32.6.13 Synchronization
    843
- 32.7 Register Summary
  845
- 32.8 Register Description
  847
  - 32.8.1 Control A
    848
  - 32.8.2 Reference Control
    849
  - 32.8.3 Average Control
    850
  - 32.8.4 Sampling Time Control
    851
  - 32.8.5 Control B
    852
  - 32.8.6 Window Monitor Control
    854
  - 32.8.7 Software Trigger
    855
  - 32.8.8 Input Control
    856
  - 32.8.9 Event Control
    860
  - 32.8.10 Interrupt Enable Clear
    861
  - 32.8.11 Interrupt Enable Set
    862
  - 32.8.12 Interrupt Flag Status and Clear
    863
  - 32.8.13 Status
    864
  - 32.8.14 Result
    865
  - 32.8.15 Window Monitor Lower Threshold
    866
  - 32.8.16 Window Monitor Upper Threshold
    867
  - 32.8.17 Gain Correction
    868
  - 32.8.18 Offset Correction
    869
  - 32.8.19 Calibration
    870
  - 32.8.20 Debug Control
    871
33. AC – Analog Comparators
872
- 33.1 Overview
  872
- 33.2 Features
  872
- 33.3 Block Diagram
  873
- 33.4 Signal Description
  873
- 33.5 Product Dependencies
  873
  - 33.5.1 I/O Lines
    873
  - 33.5.2 Power Management
    874
  - 33.5.3 Clocks
    874
  - 33.5.4 DMA
    874
  - 33.5.5 Interrupts
    874
  - 33.5.6 Events
    874
  - 33.5.7 Debug Operation
    874
  - 33.5.8 Register Access Protection
    874
  - 33.5.9 Analog Connections
    874
  - 33.5.10 Other Dependencies
    875
- 33.6 Functional Description
  875
  - 33.6.1 Principle of Operation
    875
  - 33.6.2 Basic Operation
    875
  - 33.6.3 Selecting Comparator Inputs
    877
  - 33.6.4 Window Operation
    877
  - 33.6.5 Voltage Doubler
    878
  - 33.6.6 VDDANA Scaler
    878
  - 33.6.7 Input Hysteresis
    879
  - 33.6.8 Propagation Delay vs. Power Consumption
    879
  - 33.6.9 Filtering
    879
  - 33.6.10 Comparator Output
    880
  - 33.6.11 Offset Compensation
    880
- 33.7 Additional Features
  881
  - 33.7.1 DMA Operation
    881
  - 33.7.2 Interrupts
    881
  - 33.7.3 Events
    881
  - 33.7.4 Sleep Mode Operation
    882
    - 33.7.4.1 Continuous Measurement during Sleep
      882
    - 33.7.4.2 Single-Shot Measurement during Sleep
      882
  - 33.7.5 Synchronization
    883
- 33.8 Register Summary
  884
- 33.9 Register Description
  885
  - 33.9.1 Control A
    886
  - 33.9.2 Control B
    887
  - 33.9.3 Event Control
    888
  - 33.9.4 Interrupt Enable Clear
    889
  - 33.9.5 Interrupt Enable Set
    890
  - 33.9.6 Interrupt Flag Status and Clear
    891
  - 33.9.7 Status A
    892
  - 33.9.8 Status B
    893
  - 33.9.9 Status C
    894
  - 33.9.10 Window Control
    895
  - 33.9.11 Comparator Control n
    896
  - 33.9.12 Scaler n
    900
34. DAC – Digital-to-Analog Converter
901
- 34.1 Overview
  901
- 34.2 Features
  901
- 34.3 Block Diagram
  901
- 34.4 Signal Description
  901
- 34.5 Product Dependencies
  902
  - 34.5.1 I/O Lines
    902
  - 34.5.2 Power Management
    902
  - 34.5.3 Clocks
    902
  - 34.5.4 DMA
    902
  - 34.5.5 Interrupts
    902
  - 34.5.6 Events
    902
  - 34.5.7 Debug Operation
    902
  - 34.5.8 Register Access Protection
    902
  - 34.5.9 Analog Connections
    903
- 34.6 Functional Description
  903
  - 34.6.1 Principle of Operation
    903
  - 34.6.2 Basic Operation
    903
  - 34.6.3 Additional Features
    903
    - 34.6.3.1 Conversion Range
      903
    - 34.6.3.2 DAC as an Internal Reference
      903
    - 34.6.3.3 Data Buffer
      904
    - 34.6.3.4 Voltage Pump
      904
    - 34.6.3.5 Sampling Period
      904
  - 34.6.4 DMA, Interrupts and Events
    904
    - 34.6.4.1 DMA Operation
      904
    - 34.6.4.2 Interrupts
      905
    - 34.6.4.3 Events
      905
  - 34.6.5 Sleep Mode Operation
    905
  - 34.6.6 Synchronization
    905
- 34.7 Register Summary
  907
- 34.8 Register Description
  908
  - 34.8.1 Control A
    909
  - 34.8.2 Control B
    910
  - 34.8.3 Event Control
    911
  - 34.8.4 Interrupt Enable Clear
    912
  - 34.8.5 Interrupt Enable Set
    913
  - 34.8.6 Interrupt Flag Status and Clear
    914
  - 34.8.7 Status
    915
  - 34.8.8 Data
    916
  - 34.8.9 Data Buffer
    917
35. PTC - Peripheral Touch Controller
918
- 35.1 Overview
  918
- 35.2 Features
  918
- 35.3 Block Diagram
  919
- 35.4 Signal Description
  920
- 35.5 Product Dependencies
  920
  - 35.5.1 I/O Lines
    920
  - 35.5.2 Clocks
    921
- 35.6 Functional Description
  922
36. Electrical Characteristics
923
- 36.1 Disclaimer
  923
- 36.2 Absolute Maximum Ratings
  923
- 36.3 General Operating Ratings
  925
- 36.4 Supply Characteristics
  926
- 36.5 Maximum Clock Frequencies
  926
- 36.6 Power Consumption
  929
- 36.7 Peripheral Power Consumption
  932
  - 36.7.1 All peripheral except USB
    932
  - 36.7.2 USB Peripheral Power Consumption
    933
- 36.8 I/O Pin Characteristics
  936
  - 36.8.1 Normal I/O Pins
    936
  - 36.8.2 I2C Pins
    937
  - 36.8.3 XOSC Pin
    937
  - 36.8.4 XOSC32 Pin
    937
  - 36.8.5 External Reset Pin
    937
- 36.9 Analog Characteristics
  938
- 36.10 NVM Characteristics
  950
- 36.11 Oscillators Characteristics
  951
- 36.12 PTC Typical Characteristics
  957
- 36.13 USB Characteristics
  961
- 36.14 Timing Characteristics
  962
  - 36.14.1 External Reset
    962
  - 36.14.2 SERCOM in SPI Mode Timing
    962
  - 36.14.3 SERCOM in I2C Mode Timing
    965
  - 36.14.4 SWD Timing
    967
37. Packaging Information
968
- 37.1 Thermal Considerations
  968
  - 37.1.1 Thermal Resistance Data
    968
  - 37.1.2 Junction Temperature
    968
- 37.2 Package Drawings
  969
  - 37.2.1 64-pin TQFP
    969
  - 37.2.2 64-pin QFN
    970
  - 37.2.3 48-pin TQFP
    971
  - 37.2.4 48-pin QFN
    972
  - 37.2.5 32-pin TQFP
    973
  - 37.2.6 32-pin QFN
    974
- 37.3 Soldering Profile
  975
38. Schematic Checklist
976
- 38.1 Introduction
  976
- 38.2 Power Supply
  976
  - 38.2.1 Power Supply Connections
    976
- 38.3 External Analog Reference Connections
  977
- 38.4 External Reset Circuit
  979
- 38.5 Unused or Unconnected Pins
  979
- 38.6 Clocks and Crystal Oscillators
  980
- 38.7 Programming and Debug Ports
  983
- 38.8 USB Interface
  987
39. Errata
989
- 39.1 Revision A
  989
  - 39.1.1 Device
    989
  - 39.1.2 PM
    990
  - 39.1.3 DFLL48M
    990
  - 39.1.4 FDPLL
    991
  - 39.1.5 NVMCTRL
    991
  - 39.1.6 SERCOM
    991
  - 39.1.7 USB
    991
  - 39.1.8 TCC
    992
- 39.2 Revision B
  993
  - 39.2.1 Device
    993
  - 39.2.2 PM
    994
  - 39.2.3 DFLL48M
    994
  - 39.2.4 NVMCTRL
    995
  - 39.2.5 SERCOM
    995
  - 39.2.6 TCC
    995
- 39.3 Revision C
  997
  - 39.3.1 Device
    997
  - 39.3.2 PM
    998
  - 39.3.3 DFLL48M
    998
  - 39.3.4 NVMCTRL
    998
  - 39.3.5 SERCOM
    998
  - 39.3.6 TCC
    999
- 39.4 Revision E
  1000
  - 39.4.1 Device
    1000
  - 39.4.2 DFLL48M
    1000
40. About This Document
1002
- 40.1 Conventions
  1002
  - 40.1.1 Numerical Notation
    1002
  - 40.1.2 Memory Size and Type
    1002
  - 40.1.3 Frequency and Time
    1002
  - 40.1.4 Registers and Bits
    1003
- 40.2 Acronyms and Abbreviations
  1003
41. Datasheet Revision History
1006
- 41.1 Rev. C – 07/2014
  1006
- 41.2 Rev. B – 07/2014
  1006
- 41.3 Rev. A – 02/2014
  1010
Table of Contents
1011

Ficha De Dados (ATSAMD21-XPRO)

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10 MB
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1018
Language:

English