Linear Technology DC934A - LTC2607 Dual 16-bit, I²C Vout DAC (req DC590) DC934A DC934A Ficha De Dados
Códigos do produto
DC934A
LTC2607/LTC2617/LTC2627
26071727fa
operation
specifications. For an I
2
C bus operating in the fast mode,
an active pull-up will be necessary if the bus capacitance is
greater than 200pF. The V
CC
power should not be removed
from the LTC2607/LTC2617/LTC2627 when the I
2
C bus
is active to avoid loading the I
2
C bus lines through the
internal ESD protection diodes.
The LTC2607/LTC2617/LTC2627 are receive-only (slave)
The LTC2607/LTC2617/LTC2627 are receive-only (slave)
devices. The master can write to the LTC2607/LTC2617/
LTC2627. The LTC2607/LTC2617/LTC2627 do not respond
to a read from the master.
The START (S) and STOP (P) Conditions
When the bus is not in use, both SCL and SDA must be
When the bus is not in use, both SCL and SDA must be
high. A bus master signals the beginning of a communica-
tion to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I
2
C device.
Acknowledge
The Acknowledge signal is used for handshaking between
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the lat-
est byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releases the SDA line (HIGH) during the Acknowledge clock
pulse. The slave-receiver must pull down the SDA bus line
during the Acknowledge clock pulse so that it remains a
stable LOW during the HIGH period of this clock pulse.
The LTC2607/LTC2617/LTC2627 respond to a write by a
master in this manner. The LTC2607/LTC2617/LTC2627
do not acknowledge a read (retains SDA HIGH during the
period of the Acknowledge clock pulse).
Chip Address
The state of CA0, CA1 and CA2 decides the slave address
The state of CA0, CA1 and CA2 decides the slave address
of the part. The pins CA0, CA1 and CA2 can be each set
to any one of three states: V
CC
, GND or float. This results
Power-On Reset
The LTC2607/LTC2617/LTC2627 clear the outputs to
The LTC2607/LTC2617/LTC2627 clear the outputs to
zero scale when power is first applied, making system
initialization consistent and repeatable. The LTC2607-1/
LTC2617-1/LTC2627-1 set the voltage outputs to midscale
when power is first applied.
For some applications, downstream circuits are active
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2607/
LTC2617/LTC2627 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 9) should be kept within the range
The voltage at REF (Pin 9) should be kept within the range
–0.3V ≤ V
REF
≤ V
CC
+ 0.3V (see Absolute Maximum Rat-
ings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 8) is in transition.
Transfer Function
The digital-to-analog transfer function is:
The digital-to-analog transfer function is:
V
k
V
V
V
OUT IDEAL
N
REF
REFLO
REFLO
(
)
=
−
(
)
+
2
where k is the decimal equivalent of the binary DAC
input code, N is the resolution and V
REF
is the voltage at
REF (Pin 6).
Serial Digital Interface
The LTC2607/LTC2617/LTC2627 communicate with a
The LTC2607/LTC2617/LTC2627 communicate with a
host using the standard 2-wire I
2
C interface. The Timing
Diagrams (Figures 1 and 2) show the timing relationship
of the signals on the bus. The two bus lines, SDA and
SCL, must be high when the bus is not in use. External
pull-up resistors or current sources are required on these
lines. The value of these pull-up resistors is dependent
on the power supply and can be obtained from the I
2
C