Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados
Códigos do produto
MEGA328P-XMINI
103
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
15.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk
T0
) is therefore shown as a clock enable
signal in the following figures. The figures include information on when interrupt flags are set.
contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX
value in all modes other than phase correct PWM mode.
value in all modes other than phase correct PWM mode.
Figure 15-8.
Timer/Counter Timing Diagram, no Prescaling
shows the same timing data, but with the prescaler enabled.
Figure 15-9.
Timer/Counter Timing Diagram, with Prescaler (f
clk_I/O
/8)
mode, where OCR0A is TOP.
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O
/8)
shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode where
OCR0A is TOP.
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O
/8)