Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Ficha De Dados

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in 
SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in 
software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that 
an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is 
described in 

Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 
unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further 
software updates might be impossible. If it is not necessary to change the Boot Loader software itself, it is 
recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software 
changes.

During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. 
The user software itself must prevent that this section is addressed during the self programming operation. The 
RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the Interrupt 
Vector table should be moved to the BLS as described in 

, or the interrupts must 

be disabled. Before addressing the RWW section after the programming is completed, the user software must 
clear the RWWSB by writing the RWWSRE. See 

 for an example.

To set the Boot Loader Lock bits and general Lock Bits, write the desired data to R0, write “X0001001” to 
SPMCSR and execute SPM within four clock cycles after writing SPMCSR.

See 

 and 

 for how the different settings of the Boot Loader bits affect the Flash access.

If bits 5...0 in R0 are cleared (zero), the corresponding Lock bit will be programmed if an SPM instruction is 
executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during 
this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for 
reading the lO

ck

 bits). For future compatibility it is also recommended to set bits 7 and 6 in R0 to “1” when writing 

the Lock bits. When programming the Lock bits the entire Flash can be read during the operation.

Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and 
Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the 
user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the 
SPMCSR Register.

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 
0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three 
CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in 
the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits 

Bit

7

6

5

4

3

2

1

0