Hitachi hard disk 0J11285 500 GB 2.5 " 8 MB 0J11285 Ficha De Dados

Z5K500 OEM Specifications 

44 

11.5  Error Register   

Error Register 

7 6 5 4 3 2 1 0 

CRC UNC  0  IDNF  0  ABRT 

TK0NF 

AMNF 

Table 27 Error Register   

This register contains status from the last command executed by the device, or a diagnostic code.   

At the completion of any command except Execute Device Diagnostic, the contents of this register are 
valid always even if ERR=0 in the Status Register.   

Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register 
contains a diagnostic code. See “Table 31 Diagnostic Codes” on Page 47 for the definition.   

Bit Definitions 

  

ICRCE (CRC) 

Interface CRC Error. CRC=1 indicates a CRC error has occurred on the data bus 
during a Ultra-DMA transfer. 

UNC 

Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been 
encountered. 

IDNF (IDN) 

ID Not Found. IDN=1 indicates the requested sector’s ID field could not be found. 

ABRT (ABT) 

Aborted Command. ABT=1 indicates the requested command has been aborted due 
to a device status error or an invalid parameter in an output register. 

TK0NF (T0N) 

Track 0 Not Found. T0N=1 indicates track 0 was not found during a Recalibrate 
command. 

AMNF (AMN) 

Address Mark Not Found. AMN=1 indicates the data address mark has not been 
found after finding the correct ID field for the requested sector. 
This bit is obsolete. 

11.6

11.7

11.8

11.9

Features Register   

This register is command specific. This is used with the Set Features command, S.M.A.R.T. Function Set 
command and Format Unit command.   

 

LBA High Register   

This register contains Bits 16-23. At the end of the command, this register is updated to reflect the current 
LBA Bits 16-23.   

When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits 16-23, 
and the “previous content” contains Bits 40-47. The 48-bit Address feature set is described in “12.12 
48-bit Address Feature Set”. 

 

LBA Low Register   

This register contains Bits 0-7. At the end of the command, this register is updated to reflect the current 
LBA Bits 0-7.   

When 48-bit commands are used, the “most recently written” content contains LBA Bits 0-7, and the 
“previous content” contains Bits 24-31.   

 

LBA Mid Register   

This register contains Bits 8-15. At the end of the command, this register is updated to reflect the current 
LBA Bits 8-15.   

When 48-bit addressing commands are used, the “most recently written” content contains LBA Bits 8-15, 
and the “previous content” contains Bits 32-39.