Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

101

The input buffers in both client and host models must use a Schmitt-triggered input 

design for improved noise immunity. Use 

 as a guide for input buffer design.

The processor timings specified in this section are defined at the processor pads. 

Therefore, proper simulation of the signals is the only means to verify proper timing 

and signal quality. 

See 

 for the processor pin listings and 

 for signal definitions. 

 list the AC specifications associated with the processor.

The timings specified in this section should be used in conjunction with the processor 

signal integrity models provided by Intel. 

Ensure to read all notes associated with a particular timing parameter.

Ileak075

leakage current @ 0.75*V

CCIO

-

0.13

mA

Ileak100

leakage current @ V

CCIO

-

0.10

mA

1.

V

CCIO 

supplies the PECI interface. PECI behavior does not affect V

TT

 min/max specifications.

2.

The leakage specification applies to powered devices on the PECI bus.

3.

The PECI buffer internal pull up resistance measured at 0.75*V

CCIO

Minimum V

P

Maximum V

P

Minimum V

N

Maximum V

N

PECI High Range

PECI Low Range

Valid Input
Signal Range

Minimum
Hysteresis

V

TTD

PECI Ground