Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

107

UI

Unit Interval (Gen 1)

399.88

400.12

ps

3,4 for Tx, 5 

for Rx

Unit Interval (Gen 2)

199.94

200.06

ps

T

TX-EYE

Minimum Transmission Eye Width

0.75

UI

6,7,8,9,10

T

TX-RISE/FALL

D+/D- TX Out put Rise/Fall time 

(Gen 1)

0.125

UI

7,11 

D+/D- TX Out put Rise/Fall time 

(Gen 2)

0.15

UI

T

RX-EYE

Minimum Receiver Eye Width 
(Gen 1)

0.4

UI

12,14

T

RX-TJ-CC

Max Rx Inherent Timing Error 
(Gen 2)

0.40

UI

2,13

1.

See the PCI Express Base Specification for details.

2.

Max Rx inherent total timing error for common Refclk Rx architecture. 

3.

The specified UI is equivalent to a tolerance of ±300 ppm for each Refclk source. Period does not account for SSC 

induced variations.

4.

SSC permits a +0, - 5000 ppm modulation of the clock frequency at a modulation rate not to exceed 33 kHz.

5.

UI does not account for SSC caused variations.

6.

Does not include SSC or Refclk jitter. Includes Rj at 10^

-12

. 2.5 GT/s and 5.0 GT/s use different jitter determination 

methods.

7.

Measurements at 5.0 GT/s require an oscilloscope with a bandwidth of >= 12.5 GHz, or equivalent, while 

measurements made at 2.5 GT/s require a scope with at least 6.2 GHz bandwidth. Measurement at 

5.0 GT/s must de convolve effects of compliance test board to yield an effective measurement at Tx pins. 2.5 GT/s may 

be measured within 200 mils of Tx device’s pins, although de convolution is recommended. For measurement setup 

details, see the PCI Express Base Specification. At least 10^

6

 UI of data must be acquired.

8.

Transmitter jitter is measured by driving the Transmitter under test with a low jitter “ideal” clock and connecting the 

DUT to a reference load.

9.

Transmitter raw jitter data must be convolved with a filtering function that represents the worst case CDR tracking BW. 

2.5 GT/s and 5.0 GT/s use different filter functions that are defined in the PCI Express Base Specification. After the 

convolution process has been applied, the center of the resulting eye must be determined and used as a reference point 

for obtaining eye voltage and margins.

10.

For 5.0 GT/s, de-emphasis timing jitter must be removed. An additional HPF function must be applied as shown in the 

PCI Express Base Specification. This parameter is measured by accumulating a record length of 10^6 UI while the DUT 

outputs a compliance pattern. TMIN-PULSE is defined to be nominally 1 UI wide and is bordered on both sides by pulses 

of the opposite polarity. See the PCI Express Base Specification for more details.

11.

Measured differentially from 20% to 80% of swing.

12.

Receiver eye margins are defined into a 2 x 50 Ω reference load. A Receiver is characterized by driving it with a signal 

whose characteristics are defined by the parameters specified in the PCI Express Base Specification.

13.

The four inherent timing error parameters are defined for the convenience of Rx designers, and they are measured 

during Receiver tolerancing.

14.

Minimum eye time at Rx pins to yield a 10^

-12

 BER.