Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

109

 are used in conjunction with the AC timing tables, 

.

For 

, the following notes apply:

1.  All common clock AC timings signals are referenced to the Crossing Voltage 

(V

CROSS

) of the BCLK, BCLK# at rising edge of BCLK.

2. All source synchronous AC timings are referenced to their associated strobe 

(address or data). Source synchronous data signals are referenced to the falling 

edge of their associated data strobe. Source synchronous address signals are 

referenced to the rising and falling edge of their associated address strobe.

3. All AC timings for the TAP signals are referenced to the TCK at 0.5 * V

CCIO

 at the 

processor balls. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.5 * 

V

CCIO

 at the processor die (pads).

4. All CMOS signal timings are referenced at 0.5 * V

CCIO

 at the processor pins.

VIDSCLK period

38.90

-

ns

VIDSOUT output valid delay wrt to BCLK

1.20

9.60

ns

VIDSOUT output jitter

-3.60

0.65

ns

3

VIDSOUT input setup time 

1.00

-

ns

3,4

VIDSOUT input hold time 

3.00

-

ns

3,4

VIDSCLK High Time

12.00

-

ns

5

VIDSCLK Low Time 

12.00

-

ns

6

VIDSCLK Rise Time 

-

2.50

ns

7

VIDSCLK Fall Time 

-

2.50

ns

8

Duty Cycle

45.00

55.00

%

1.

See the voltage regulator design guidelines for additional information.

2.

Platform support for SVID transitions is required for the processor to operate within specifications.

3.

Referenced to rising edge of VIDSCLK.

4.

Minimum edge rate of 0.5V/nS.

5.

High time is measured with respect to 0.3 * VCCIO.

6.

Low time is measured with respect to 0.7 * VCCIO.

7.

Rise time is measured from 0.3 * VCCIO to 0.7 * VCCIO.

8.

Fall time is measured 0.7 * VCCIO to 0.3 * VCCIO.

9.

Period and duty cycle are measured with respect to 0.5 * VCCIO.