Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

156

Document Number: 327405

-

001

Once the error flag bits are set as a result of an error, this bit field is locked and doesn't 

change as a result of a new error until the error flag is cleared by software. Same is the 

case with error syndrome field.

B/D/F/Type:

0/0/0/MCHBAR MC0

Address Offset:

40CC-40CFh

Default Value:

00000000h

Access:

ROS-V

Size:

32 bits

This register is used to store the error status information in ECC enabled 

configurations, along with the error syndrome and the row and column address 

information of the address block of main memory of which an error (single bit or multi-

bit error) has occurred.

31:29

ROS-V

000b

Powergood

Error Bank Address (ERRBANK):
This field holds the Bank Address of the read 

transaction that had the ECC error.

28:27

ROS-V

00b

Powergood

Error Rank Address (ERRRANK):
This field holds the Rank ID of the read transaction 

that had the ECC error.

26:24

ROS-V

000b

Powergood

Error Chunk (ERRCHUNK):
Holds the chunk number of the error stored in the 

register.

23:16

ROS-V

00h

Powergood

Error Syndrome (ERRSYND):
This field contains the error syndrome. A value of FFh 

indicates that the error is due to poisoning.

For ERRSYND definition see 

15:2

RO

0h

Reserved (RSVD) 

1

ROS-V

0b

Powergood

Multiple Bit Error Status (MERRSTS):
This bit is set when an uncorrectable multiple-bit error 

occurs on a memory read data transfer. When this bit 

is set, the address that caused the error and the error 

syndrome are also logged and they are locked until 

this bit is cleared.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.

0

ROS-V

0b

Powergood

Correctable Error Status (CERRSTS):
This bit is set when a correctable single-bit error 

occurs on a memory read data transfer. When this bit 

is set, the address that caused the error and the error 

syndrome are also logged and they are locked to 

further single bit errors, until this bit is cleared.
A multiple bit error that occurs after this bit is set will 

override the address/error syndrome information.
This bit is cleared when the corresponding bit in 

0.0.0.PCI.ERRSTS is cleared.