Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

158

Document Number: 327405

-

001

B/D/F/Type:

0/0/0/MCHBAR MC1

Address Offset:

44CC-44CFh

Default Value:

00000000h

Access:

ROS-V

Size:

32 bits

This register is used to store the error status information in ECC enabled 

configurations, along with the error syndrome and the row and column address 

information of the address block of main memory of which an error (single bit or multi-

bit error) has occurred.

B/D/F/Type:

0/0/0/MCHBAR_MCMAIN

Address Offset:

5004-5007h

Default Value:

00600000h

Access:

RW-L

1

RO-P

0b

Powergood

Multiple Bit Error Status (MERRSTS):
This bit is set when an uncorrectable multiple-bit error 

occurs on a memory read data transfer. When this bit 

is set, the address that caused the error and the error 

syndrome are also logged and they are locked until 

this bit is cleared.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.

0

RO-P

0b

Powergood

Correctable Error Status (CERRSTS):
This bit is set when a correctable single-bit error 

occurs on a memory read data transfer. When this bit 

is set, the address that caused the error and the error 

syndrome are also logged and they are locked to 

further single bit errors, until this bit is cleared.
A multiple bit error that occurs after this bit is set will 

override the address/error syndrome information.
This bit is cleared when the corresponding bit in 

0.0.0.PCI.ERRSTS is cleared.

31:16

ROS-V

0000h

Powergood

Error Column (ERRCOL):
This field holds the DRAM column address of the 

read transaction that had the ECC error.

15:0

ROS-V

0000h

Powergood

Error Row (ERRROW):
This field holds the DRAM row (page) address of 

the read transaction that had the ECC error.