Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

58

Document Number: 327405

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001

1. No power-down.
2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is 

the bank status.

3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters 

powerdown.

4. DLL-off: same as option (2) but DDR is configured to DLL-off.
5. APD, change to PPD (APD-PPD): Begins as option (1), and when all page-close 

timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to 

PPD.

6. APD, change to DLL-off (APD_DLLoff) – Begins as option (1), and when all page-

close timers of the rank are expired, it wakes the rank, issues PRE-all and returns 

to DLL-off power-down.

The CKE is determined per rank when it is inactive. Each rank has an idle-counter. The 

idle-counter starts counting as soon as the rank has no accesses, and if it expires, the 

rank may enter power-down while no new transactions to the rank arrive to queues. 

The idle-counter begins counting at the last incoming transaction arrival. 

It is important to understand that since the power-down decision is per rank, the MC 

can find many opportunities to power-down ranks even while running memory 

intensive applications, and savings are significant (may be a few watts, according to 

the DDR specification). This is significant when each channel is populated with more 

ranks.

Selection of power modes should be according to power-performance or thermal 

tradeoffs of a given system:

• When trying to achieve maximum performance and power or thermal consideration 

is not an issue: use no power-down.

• In a system that tries to minimize power-consumption, try to use the deepest 

power-down mode possible – DLL-off or APD_DLLoff.

• In high-performance systems with dense packaging (that is, complex thermal 

design) the power-down mode should be considered in order to reduce the heating 

and avoid DDR throttling caused by the heating.

Control of the power-mode must be controlled through the BIOS – The BIOS selects 

no-powerdown by default. There are knobs to change the power-down selected mode.

Another control is the idle timer expiration count. This is set through PM_PDWN_config 

bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the MC will have more 

opportunities to put DDR in power-down. The minimum recommended value for this 

register is 15. There is no BIOS hook to set this register. Customers who choose to 

change the value of this register can do it by changing the BIOS. For experiments, this 

register can be modified in real time if BIOS did not lock the MC registers.

In APD, APD-PPD, and APD_DLL-off, there is no point in setting the idle-counter in the 

same range as page-close idle timer. 

Another option associated with CKE power-down is the S_DLL-off. When this option is 

enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do 

not confuse it with the DLL-off mode in which the DDR DLLs are off). This mode 

requires you to define the I/O slave DLL wakeup time.