Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

59

During power-up, CKE is the only input to the SDRAM that has its level is recognized 

(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the 

DDR controller to make sure the SDRAM components float DQ and DQS during power-

up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a 

configuration register. Using this method, CKE is guaranteed to remain inactive for 

much longer than the specified 200 micro-seconds after power and clocks to SDRAM 

devices are stable.

Dynamic power-down of memory is employed during normal operation. Based on idle 

conditions, a given memory rank may be powered down. The IMC implements 

aggressive CKE control to dynamically put the DRAM devices in a power down state. 

The processor core controller can be configured to put the devices in active power-

down (CKE deassertion with open pages) or precharge power-down (CKE deassertion 

with all pages closed). Precharge power-down provides greater power savings but has 

a bigger performance impact, since all pages will first be closed before putting the 

devices in power-down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh 

cycle and all ranks are powered down at the end of refresh.

Unused signals should be disabled to save power and reduce electromagnetic 

interference. This includes all signals associated with an unused memory channel. 

Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM 

control signals such as CS#, CKE, and ODT for unpopulated DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the 

input receiver (differential sense-amp) should be disabled, and any DLL circuitry 

related ONLY to unused signals should be disabled. The input path must be gated to 

prevent spurious results due to noise on the unused signals (typically handled 

automatically when input receiver is disabled).

• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.

PCIe* interface does not support Hot Plug.

Power impact may be observed when PCIe* link disable power management state is 

used.

Active power management support using L0s/L1 state.

See 

 for all thermal power 

management-related features.