Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

71

This chapter describes the processor signals. They are arranged in functional groups 

according to their associated interface or category. The following notations are used to 

describe the signal type:

The signal description also includes the type of buffer used for the particular signal.

I

Input  Pin

O

Output  Pin

I/O

Bi-directional Input/Output Pin

PCI Express*

PCI Express* interface signals. These signals are compatible with PCI Express* 2.0 

Signalling Environment AC Specifications and are AC coupled. The buffers are not 3.3-

V tolerant. See the PCIe* specification.

DMI

Direct Media Interface signals. These signals are compatible with PCI Express* 2.0 

Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3-

V tolerant.

CMOS

CMOS buffers. 1.1-V tolerant

DDR3

DDR3 buffers: 1.5-V tolerant

A

Analog reference or output. May be used as a threshold voltage or for buffer 

compensation

Ref

Voltage reference signal

Asynchronous

Signal has no timing relationship with any reference clock.

1.

Qualifier for a buffer type.

SA_BS[2:0]

Bank Select: These signals define which banks 

are selected within each SDRAM rank.

O

DDR3

SA_WE#

Write Enable Control Signal: Used with 

SA_RAS# and SA_CAS# (along with SA_CS#) to 

define the SDRAM Commands.

O

DDR3

SA_RAS#

RAS Control Signal: Used with SA_CAS# and 

SA_WE# (along with SA_CS#) to define the SRAM 

Commands.

O

DDR3