Intel E3-1105C AV8062701048800 Ficha De Dados

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

73

SB_CAS#

CAS Control Signal: Used with SB_RAS# and 

SB_WE# (along with SB_CS#) to define the SRAM 

Commands.

O

DDR3

SB_DQS[7:0] SB_DQS#[7:0]

Data Strobes: SB_DQS[7:0] and its complement 

signal group make up a differential strobe pair. The 

data is captured at the crossing point of 

SB_DQS[7:0] and its SB_DQS#[7:0] during read 

and write transactions.

I/O

DDR3 

SB_DQS[8] 

SB_DQS#[8]

Data Strobes: SB_DQS[8] is the data strobe for 

the ECC check data bits SB_DQ[71:64]. 

SB_DQS#[8] is the complement strobe for the ECC 

check data bits SB_DQ[71:64]
The data is captured at the crossing point of 

SB_DQS[8:0] and its SB_DQS#[8:0] during read 

and write transactions.
Note: Not required for non-ECC mode 

I/O

DDR3 

SB_DQ[63:0]

Data Bus: Channel B data signal interface to the 

SDRAM data bus.

I/O

DDR3 

SB_ECC_CB[7:0]

ECC Data Lines: Data Lines for ECC Check Byte 

for Channel B.
Note: Not required for non-ECC mode

I/O

DDR3 

SB_MA[15:0]

Memory Address: These signals are used to 

provide the multiplexed row and column address to 

the SDRAM.

O

DDR3

SB_CK[3:0]

SB_CK#[3:0]

SDRAM Differential Clock: Channel B SDRAM 

Differential clock signal pair. The crossing of the 

positive edge of SB_CK and the negative edge of its 

complement SB_CK# are used to sample the 

command and control signals on the SDRAM.

O

DDR3

SB_CKE[3:0]

Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-refresh 

during STR.

O

DDR3

SB_CS#[3:0]

Chip Select: (1 per rank) Used to select particular 

SDRAM components during the active state. There 

is one Chip Select for each SDRAM rank.

O

DDR3

SB_ODT[3:0]

On Die Termination: Active Termination Control.

O

DDR3