Renesas M32R-FPU Manual Do Utilizador

3

3-69

M32R-FPU Software Manual (Rev.1.01)

DSP function instruction

Multiply and add

accumulator += (( signed) (Rsrc1 & 0xffff0000) * (signed short) (Rsrc2 >> 16));

MACHI multiplies the high-order 16 bits of Rsrc1 and the high-order 16 bits of Rsrc2, then adds

the result to the low-order 56 bits in the accumulator.

The LSB of the multiplication result is aligned with bit 47 in the accumulator, and the portion

corresponding to bits 8 through 15 of the accumulator is sign-extended before addition. The

result of the addition is stored in the accumulator. The high-order 16 bits of Rsrc1 and Rsrc2 are

treated as signed values.

The condition bit (C) is unchanged.

None

Rsrc1

high-order 16 bits

Rsrc2

high-order 16 bits

x

0

15 16

31

0

Result of the multiplication

Value in accumulator before the
execution of the MACHI instruction

Value in accumulator after the
execution of the MACHI instruction

Sign extension

Sign extension

+

0

15 16

31 32

47 48

63

7 8

INSTRUCTIONS

3.2 Instruction description