Manuais de utilizador para Renesas M32R-FPU

índice analítico

• REVISION HISTORY

  3
• Table of contents

  4
• CHAPTER 1 CPU PROGRAMMIING MODEL

  7
  • 1.1 CPU Register

    8
  • 1.2 General-purpose Registers

    8
  • 1.3 Control Registers

    9
    • 1.3.1 Processor Status Word Register: PSW (CR0)

      10
    • 1.3.2 Condition Bit Register: CBR (CR1)

      11
    • 1.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3)

      11
    • 1.3.4 Backup PC: BPC (CR6)

      11
    • 1.3.5 Floating-point Status Register: FPSR (CR7)

      12
    • 1.3.6 Floating-point Exceptions (FPE)

      14
  • 1.4 Accumulator

    17
  • 1.5 Program Counter

    17
  • 1.6 Data Format

    18
    • 1.6.1 Data Type

      18
    • 1.6.2 Data Format

      19
  • 1.7 Addressing Mode

    21
• CHAPTER 2 INSTRUCTION SET

  23
  • 2.1 Instruction set overview

    24
    • 2.1.1 Load/store instructions

      24
    • 2.1.2 Transfer instructions

      26
    • 2.1.3 Operation instructions

      26
    • 2.1.4 Branch instructions

      28
    • 2.1.5 EIT-related instructions

      30
    • 2.1.6 DSP function instructions

      30
    • 2.1.7 Floating-point Instructions

      33
    • 2.1.8 Bit Operation Instructions

      33
  • 2.2 Instruction format

    34
• CHAPTER 3 INSTRUCTIONS

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  • 3.1 Conventions for instruction description

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  • 3.2 Instruction description

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    • ADD

      42
    • ADD3

      43
    • ADDI

      44
    • ADDV

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    • ADDV3

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    • ADDX

      47
    • AND

      48
    • AND3

      49
    • BC

      50
    • BCLR

      51
    • BEQ

      52
    • BEQZ

      53
    • BGEZ

      54
    • BGTZ

      55
    • BL

      56
    • BLEZ

      57
    • BLTZ

      58
    • BNC

      59
    • BNE

      60
    • BNEZ

      61
    • BRA

      62
    • BSET

      63
    • BTST

      64
    • CLRPSW

      65
    • CMP

      66
    • CMPI

      67
    • CMPU

      68
    • CMPUI

      69
    • DIV

      70
    • DIVU

      71
    • FADD

      72
    • FCMP

      74
    • FCMPE

      76
    • FDIV

      78
    • FMADD

      80
    • FMSUB

      83
    • FMUL

      86
    • FSUB

      88
    • FTOI

      90
    • FTOS

      92
    • ITOF

      94
    • JL

      95
    • JMP

      96
    • LD

      97
    • LD24

      98
    • LDB

      99
    • LDH

      100
    • LDI

      101
    • LDUB

      102
    • LDUH

      103
    • LOCK

      104
    • MACHI

      105
    • MACLO

      106
    • MACWHI

      107
    • MACWLO

      108
    • MUL

      109
    • MULHI

      110
    • MULLO

      111
    • MULWHI

      112
    • MULWLO

      113
    • MV

      114
    • MVFACHI

      115
    • MVFACLO

      116
    • MVFACMI

      117
    • MVFC

      118
    • MVTACHI

      119
    • MVTACLO

      120
    • MVTC

      121
    • NEG

      122
    • NOP

      123
    • NOT

      124
    • OR

      125
    • OR3

      126
    • RAC

      127
    • RACH

      129
    • REM

      131
    • REMU

      132
    • RTE

      133
    • SETH

      134
    • SETPSW

      135
    • SLL

      136
    • SLL3

      137
    • SLLI

      138
    • SRA

      139
    • SRA3

      140
    • SRAI

      141
    • SRL

      142
    • SRL3

      143
    • SRLI

      144
    • ST

      145
    • STB

      147
    • STH

      148
    • SUB

      149
    • SUBV

      150
    • SUBX

      151
    • TRAP

      152
    • UNLOCK

      153
    • UTOF

      154
    • XOR

      155
    • XOR3

      156
• APPENDICES

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  • Appendix1 Hexadecimal Instraction Code

    158
  • Appendix 2 Instruction List

    160
  • Appendix 3 Pipeline Processing

    164
    • Appendix 3.1 Instructions and Pipeline Processing

      164
    • Appendix 3.2 Pipeline Basic Operation

      166
  • Appendix 4 Instruction Execution Time

    173
  • Appendix 5 IEEE754 Specification Overview

    174
    • Appendix 5.1 Floating Point Formats

      174
    • Appendix 5.2 Rounding

      176
    • Appendix 5.3 Exceptions

      176
  • Appendix 6 M32R-FPU Specification Supplemental Explanation

    179
    • Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two instructions (FMUL and FADD)

      179
      • Appendix 6.1.1 Rounding Mode

        179
      • Appendix 6.1.2 Exception occurring in Step 1

        179
    • Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU

      184
  • Appendix 7 Precautions

    185
    • Appendix 7.1 Precautions to be taken when aligning data

      185
• INDEX

  187