Renesas M32R-FPU Manual Do Utilizador
3
3-94
M32R-FPU Software Manual (Rev.1.01)
[Supplement]
This instruction is executed in two steps, as shown below.
<proccess 1>
<proccess 2>
The value in the accumulator is altered depending on the supposed bit 80 through 7 after
left-shift operation and bit 8 through bit 63 after shift operation.
left-shift operation and bit 8 through bit 63 after shift operation.
if bit 32 is 0 , there is no carry.
if bit 32 is 1 , the bit is carried.
Bits 32 to 63 are cleared to zero.
if bit 32 is 1 , the bit is carried.
Bits 32 to 63 are cleared to zero.
0000 7FFE 8000 0000
positive
value
negative
value
0000 7FFE 7FFF 7FFF
0000 0000 0000 0000
FFFF 8000 8000 0000
FFFF 8000 7FFF FFFF
supposed sign
extended bit0-bit7
extended bit0-bit7
1-bit shift to the left
Value in Adest after the
execution of the RAC instruction
execution of the RAC instruction
8
63
16
32
48
00
7FFF
FFFF
0000
0
8
63
00
FF
8000
0000
0000
0
8
63
FF
31
32
8
63
0
0
48
8
0
63
0
0
••
••
••
••
••
••
••
••
••
••
16
32
48
8
0
0
63
16
32
48
8
63
47
0
sign extension
INSTRUCTIONS
3.2 Instruction description
RACH
RACH
DSP function instruction
Round accumulator halfword