Renesas M32R-FPU Manual Do Utilizador

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

1.3 Control Registers

(3) Inexact Exception (IXCT)

The exception occurs when the operation result differs from a result led out with an

infinite range of precision. The following table shows the operation results and the

respective conditions in which each IXCT occurs.

Operation Result (Content of the Destination Register)

Occurrence Condition

When the IXCT EIT processing is

masked (Note 1)

executed (Note 2)

Overflow occurs in OVF

Reference OVF operation results

No change

masked condition

Rounding occurs

Rounded value

No change

Note 1: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "0"

Note 2: When the Inexact Exception Enable (EX) bit (FPSR register bit 17) = "1"

(4) Zero Division Exception (DIV0)

The exception occurs when a finite nonzero value is divided by zero. The following

table shows the operation results when a DIV0 occurs.

Operation Result (Content of the Destination Register)

Dividend

When the DIV0 EIT processing is

masked (Note 1)

executed (Note 2)

Nonzero finite value

infinity (Sign is derived by exclusive-

No change

ORing the signs of divisor and dividend)

Note 1: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "0"

Note 2: When the Zero Division Exception Enable (EZ) bit (FPSR register bit 19) = "1"

Please note that the DIV0 EIT processing does not occur in the following conditions.

Dividend

Behavior

An invalid operation exception occurs

infinity

No exception occur (with the result "infinity")