Renesas M32R-FPU Manual Do Utilizador

APPENDICES

APPENDICES-12

M32R-FPU Software Manual (Rev.1.01)

(2) Pipeline Flow with Stalls

A pipeline stage may stall due to execution of a process or branch instruction.

The following diagrams show typical stall cases.

<Case 1>  An instruction which requires several cycles is executed in E 

IF

D

E

WB

E

E

IF

D

stall

WB

E

stall

IF

D

WB

E

stall

stall

IF

D

stall

WB

E

stall

<Case 2>  An instruction which requires more than 1 cycle for its operand access is executed

IF

D

E

WB

MEM1

IF

D

WB

E

stall

IF

D

stall

WB

E

IF

D

WB

E

stall

MEM1

MEM2

MEM1

MEM2

MEM1

stall

stall

stall

Other than no-wait 

memory access

stall: a pipeline stall

Appendix Figure 3.2.3  Pipeline Flow with Stalls (1)

APPENDIX 3

Appendix 3 Pipeline Processing