Renesas M32R-FPU Manual Do Utilizador

2-7

M32R-FPU Software Manual (Rev.1.01)

The addressing mode of the BRA, BL, BC and BNC instructions can specify an 8-bit or

24-bit immediate value. The addressing mode of the BEQ, BNE, BEQZ, BNEZ, BLTZ,

BGEZ, BLEZ, and BGTZ instructions can specify a 16-bit immediate value.

In the JMP and JL instructions, the register value becomes the branch address.

H o w e v e r , t h e l o w - o r d e r 2 - b i t v a l u e o f t h e r e g i s t e r i s i g n o r e d . I n o t h e r b r a n c h

instructions, (PC value of branch instruction) + (sign-extended and 2 bits left-shifted

immediate value) becomes the branch address. However, the low order 2-bit value of the

address becomes "00" when addition is carried out. For example, refer to Figure 2.1.1.

W h e n i n s t r u c t i o n A o r B i s a b r a n c h i n s t r u c t i o n , b r a n c h i n g t o i n s t r u c t i o n G , t h e

immediate value of either instruction A or B becomes 4.

Simultaneous with execution of branching by the JL or BL instructions for subroutine

calls, the PC value of the return address is stored in R14. The low-order 2-bit value of

the address stored in R14 (PC value of the branch instruction + 4 ) is always cleared to

"0". For example, refer to Figure 2.1.1. If an instruction A or B is a JL or BL instruction,

the return address becomes that of the instruction C.

Fig. 2.1.1 Branch addresses of branch instruction

H'00

H'04

H'08

H'0C

H'10

instruction A

instruction B

instruction C

instruction D

instruction E

instruction F

instruction G

instruction H

address

1 word (32 bits)

branch instruction

INSTRUCTION SET

2.1 Instruction set overview