Renesas M32R-FPU Manual Do Utilizador

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M32R-FPU Software Manual (Rev.1.01)

Describes the operation performed by the instruction and any condition bit change.

Shows possible EIT events (Exception, Interrupt, Trap) which may occur as the result of

the instruction's execution. Only address exception (AE), floating-point exception (FPE)

and trap (TRAP) may result from an instruction execution.

Shows the bit level instruction pattern (16 bits or 32 bits). Source and/or destination

register numbers are put in the src and dest fields as appropriate. Any immediate or

displacement value is put in the imm or disp field,  its maximum size being determined by

the width of the field provided for the particular instruction. Refer to 2.2 Instruction

format for detail.

INSTRUCTIONS

3.1 Conventions for instruction description