Renesas M32R-FPU Manual Do Utilizador

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M32R-FPU Software Manual (Rev.1.01)

CPU PROGRAMMING MODEL

1.1 CPU Register

The M32R family CPU, with a built-in FPU (herein referred to as M32R-FPU) has 16

general-purpose registers, 6 control registers, an accumulator and a program

counter. The accumulator is of 56-bit configuration, and all other registers are a 32-

bit configuration.

1.2 General-purpose Registers

The 16 general-purpose registers (R0 – R15) are of 32-bit width and are used to

retain data and base addresses, as well as for integer calculations, floating-point

operations, etc. R14 is used as the link register and R15 as the stack pointer. The link

instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are

alternately represented by R15 depending on the value of the Stack Mode (SM) bit in

the Processor Status Word Register (PSW).

At reset release, the value of the general-purpose registers is undefined.

b31

R10

R11

R12

R13

R14 (Link register)

R15 (Stack pointer)

Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW.

Figure 1.2.1 General-purpose Registers

(Note 1)