Apollo ESP6000 Manual Do Utilizador
User’s Manual
ECM-3612 User’s Manual
69
3.5.3.19 PCI Delayed Transaction
This feature is used to meet the latency of PCI cycles to and from the ISA bus. The ISA bus
is much, much slower than the PCI bus. Thus, PCI cycles to and from the ISA bus take a
longer time to complete and this slows the PCI bus down.
However, enabling Delayed Transaction enables the chipset's embedded 32-bit posted
write buffer to support delayed transaction cycles. This means that transactions to and from
the ISA bus are buffered and the PCI bus can be freed to perform other transactions while
the ISA transaction is underway.
This option should be enabled for better performance and to meet PCI 2.1 specifications.
Disable it only if your PCI cards cannot work properly or if you are using an ISA card that is
not PCI 2.1 compliant.
The choices: Enabled, Disabled.
This feature is used to meet the latency of PCI cycles to and from the ISA bus. The ISA bus
is much, much slower than the PCI bus. Thus, PCI cycles to and from the ISA bus take a
longer time to complete and this slows the PCI bus down.
However, enabling Delayed Transaction enables the chipset's embedded 32-bit posted
write buffer to support delayed transaction cycles. This means that transactions to and from
the ISA bus are buffered and the PCI bus can be freed to perform other transactions while
the ISA transaction is underway.
This option should be enabled for better performance and to meet PCI 2.1 specifications.
Disable it only if your PCI cards cannot work properly or if you are using an ISA card that is
not PCI 2.1 compliant.
The choices: Enabled, Disabled.
3.5.3.20 PCI#2 Access #1 Retry
This item is linked to the CPU to PCI write Buffer. All writes to the PCI bus are immediately
written into the buffer, instead of the PCI bus. This frees up the CPU from waiting till the PCI
bus is free. The data are then written to the PCI bus when the next PCI bus cycle starts.
The choices: Enabled, Disabled.
This item is linked to the CPU to PCI write Buffer. All writes to the PCI bus are immediately
written into the buffer, instead of the PCI bus. This frees up the CPU from waiting till the PCI
bus is free. The data are then written to the PCI bus when the next PCI bus cycle starts.
The choices: Enabled, Disabled.
3.5.3.21 AGP Master 1 WS Write
Enables this item to increase AGP writing.
The Choices: Enabled, Disabled.
Enables this item to increase AGP writing.
The Choices: Enabled, Disabled.
3.5.3.22 AGP Master 1 WS Read
Enables this item to increase AGP reading.
The choices: Enabled, Disabled.
Enables this item to increase AGP reading.
The choices: Enabled, Disabled.