Manuais de utilizador para Fujitsu F2MCTM-16LX

índice analítico

• CHAPTER 1 OVERVIEW

  17
  • 1.1 Overview of MB90360

    18
  • 1.2 Block Diagram of MB90360 series

    25
  • 1.3 Package Dimensions

    28
  • 1.4 Pin Assignment

    29
  • 1.5 Pin Functions

    30
  • 1.6 Input-Output Circuits

    33
  • 1.7 Handling Device

    37
• CHAPTER 2 CPU

  43
  • 2.1 Outline of the CPU

    44
  • 2.2 Memory Space

    45
  • 2.3 Memory Map

    48
  • 2.4 Linear Addressing

    49
  • 2.5 Bank Addressing Types

    50
  • 2.6 Multi-byte Data in Memory Space

    52
  • 2.7 Registers

    53
    • 2.7.1 Accumulator (A)

      56
    • 2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP)

      57
    • 2.7.3 Processor Status (PS)

      58
    • 2.7.4 Program Counter (PC)

      61
  • 2.8 Register Bank

    62
  • 2.9 Prefix Codes

    64
  • 2.10 Interrupt Disable Instructions

    67
  • 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions

    68
• CHAPTER 3 INTERRUPTS

  71
  • 3.1 Outline of Interrupts

    72
  • 3.2 Interrupt Vector

    75
  • 3.3 Interrupt Control Registers (ICR)

    77
  • 3.4 Interrupt Flow

    81
  • 3.5 Hardware Interrupts

    83
    • 3.5.1 Hardware Interrupt Operation

      84
    • 3.5.2 Occurrence and Release of Hardware Interrupt

      85
    • 3.5.3 Multiple interrupts

      87
  • 3.6 Software Interrupts

    88
  • 3.7 Extended Intelligent I/O Service (EI2OS)

    90
    • 3.7.1 Extended Intelligent I/O Service Descriptor (ISD)

      92
    • 3.7.2 EI2OS Status Register (ISCS)

      94
  • 3.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)

    95
  • 3.9 Exceptions

    98
• CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE

  99
  • 4.1 Overview of Delayed Interrupt Generation Module

    100
  • 4.2 Block Diagram of Delayed Interrupt Generation Module

    101
  • 4.3 Configuration of Delayed Interrupt Generation Module

    102
    • 4.3.1 Delayed interrupt request generate/cancel register (DIRR)

      103
  • 4.4 Explanation of Operation of Delayed Interrupt Generation Module

    104
  • 4.5 Precautions when Using Delayed Interrupt Generation Module

    105
  • 4.6 Program Example of Delayed Interrupt Generation Module

    106
• CHAPTER 5 CLOCKS

  107
  • 5.1 Clocks

    108
  • 5.2 Block Diagram of the Clock Generation Block

    111
    • 5.2.1 Register of Clock Generation Block

      113
  • 5.3 Clock Selection Register (CKSCR)

    114
  • 5.4 PLL/Subclock Control Register (PSCCR)

    117
  • 5.5 Clock Mode

    119
  • 5.6 Oscillation Stabilization Wait Interval

    123
  • 5.7 Connection of an Oscillator or an External Clock to the Microcontroller

    124
• CHAPTER 6 CLOCK SUPERVISOR

  125
  • 6.1 Overview of Clock Supervisor

    126
  • 6.2 Block Diagram of Clock Supervisor

    127
  • 6.3 Clock Supervisor Control Register (CSVCR)

    129
  • 6.4 Operating Mode of Clock Supervisor

    131
• CHAPTER 7 RESETS

  135
  • 7.1 Resets

    136
  • 7.2 Reset Cause and Oscillation Stabilization Wait Times

    139
  • 7.3 External Reset Pin

    141
  • 7.4 Reset Operation

    142
  • 7.5 Reset Cause Bits

    144
  • 7.6 Status of Pins in a Reset

    148
• CHAPTER 8 LOW-POWER CONSUMPTION MODE

  149
  • 8.1 Overview of Low-Power Consumption Mode

    150
  • 8.2 Block Diagram of the Low-Power Consumption Control Circuit

    153
  • 8.3 Low-Power Consumption Mode Control Register (LPMCR)

    155
  • 8.4 CPU Intermittent Operation Mode

    158
  • 8.5 Standby Mode

    159
    • 8.5.1 Sleep Mode

      161
    • 8.5.2 Watch Mode

      164
    • 8.5.3 Timebase Timer Mode

      166
    • 8.5.4 Stop Mode

      168
  • 8.6 Status Change Diagram

    171
  • 8.7 Status of Pins in Standby Mode and during Hold and Reset

    172
  • 8.8 Usage Notes on Low-Power Consumption Mode

    173
• CHAPTER 9 MEMORY ACCESS MODES

  177
  • 9.1 Outline of Memory Access Modes

    178
    • 9.1.1 Mode Pins

      179
    • 9.1.2 Mode Data

      180
    • 9.1.3 Memory Space in Each Bus Mode

      181
• CHAPTER 10 I/O PORTS

  183
  • 10.1 I/O Ports

    184
  • 10.2 I/O Port Registers

    185
    • 10.2.1 Port Data Register (PDR)

      186
    • 10.2.2 Port Direction Register (DDR)

      188
    • 10.2.3 Pull-up Control Register (PUCR)

      190
    • 10.2.4 Analog Input Enable Register (ADER)

      191
    • 10.2.5 Input Level Select Register

      192
• CHAPTER 11 TIMEBASE TIMER

  195
  • 11.1 Overview of Timebase Timer

    196
  • 11.2 Block Diagram of Timebase Timer

    198
  • 11.3 Configuration of Timebase Timer

    200
    • 11.3.1 Timebase timer control register (TBTC)

      201
  • 11.4 Interrupt of Timebase Timer

    203
  • 11.5 Explanation of Operations of Timebase Timer Functions

    204
  • 11.6 Precautions when Using Timebase Timer

    208
  • 11.7 Program Example of Timebase Timer

    209
• CHAPTER 12 WATCHDOG TIMER

  211
  • 12.1 Overview of Watchdog Timer

    212
  • 12.2 Configuration of Watchdog Timer

    215
  • 12.3 Watchdog Timer Registers

    217
    • 12.3.1 Watchdog timer control register (WDTC)

      218
  • 12.4 Explanation of Operations of Watchdog Timer Functions

    220
  • 12.5 Precautions when Using Watchdog Timer

    223
  • 12.6 Program Examples of Watchdog Timer

    224
• CHAPTER 13 16-Bit I/O TIMER

  225
  • 13.1 Overview of 16-bit I/O Timer

    226
  • 13.2 Block Diagram of 16-bit I/O Timer

    227
    • 13.2.1 Block Diagram of 16-bit Free-run Timer

      229
    • 13.2.2 Block Diagram of Input Capture

      230
  • 13.3 Configuration of 16-bit I/O Timer

    232
    • 13.3.1 Timer Control Status Register (Upper) (TCCSH)

      233
    • 13.3.2 Timer Control Status Register (Lower) (TCCSL)

      234
    • 13.3.3 Timer Data Register (TCDT)

      236
    • 13.3.4 Input Capture Control Status Registers (ICS)

      237
    • 13.3.5 Input Capture Register (IPCP)

      239
    • 13.3.6 Input Capture Edge Register (ICE)

      240
  • 13.4 Interrupts of 16-bit I/O Timer

    243
  • 13.5 Explanation of Operation of 16-bit Free-run Timer

    245
  • 13.6 Explanation of Operation of Input Capture

    247
  • 13.7 Precautions when Using 16-bit I/O Timer

    249
  • 13.8 Program Example of 16-bit I/O Timer

    250
• CHAPTER 14 16-BIT RELOAD TIMER

  253
  • 14.1 Overview of the 16-bit Reload Timer

    254
  • 14.2 Block Diagram of 16-bit Reload Timer

    256
  • 14.3 Configuration of 16-bit Reload Timer

    258
    • 14.3.1 Timer Control Status Registers (High) (TMCSR:H)

      261
    • 14.3.2 Timer Control Status Registers (Low) (TMCSR: L)

      263
    • 14.3.3 16-bit Timer Registers (TMR)

      265
    • 14.3.4 16-bit Reload Registers (TMRLR)

      266
  • 14.4 Interrupts of 16-bit Reload Timer

    267
  • 14.5 Explanation of Operation of 16-bit Reload Timer

    268
    • 14.5.1 Operation in Internal Clock Mode

      270
    • 14.5.2 Operation in Event Count Mode

      275
  • 14.6 Precautions when Using 16-bit Reload Timer

    278
  • 14.7 Sample Program of 16-bit Reload Timer

    279
• CHAPTER 15 WATCH TIMER

  283
  • 15.1 Overview of Watch Timer

    284
  • 15.2 Block Diagram of Watch Timer

    286
  • 15.3 Configuration of Watch Timer

    288
    • 15.3.1 Watch Timer Control Register (WTC)

      289
  • 15.4 Watch Timer Interrupt

    291
  • 15.5 Explanation of Operation of Watch Timer

    292
  • 15.6 Program Example of Watch Timer

    294
• CHAPTER 16 8-/16-BIT PPG TIMER

  297
  • 16.1 Overview of 8-/16-bit PPG Timer

    298
  • 16.2 Block Diagram of 8-/16-bit PPG Timer

    301
    • 16.2.1 Block Diagram for 8-/16-bit PPG Timer C

      302
    • 16.2.2 Block Diagram of 8-/16-bit PPG Timer D

      304
  • 16.3 Configuration of 8-/16-bit PPG Timer

    306
    • 16.3.1 PPGC Operation Mode Control Register (PPGCC)

      308
    • 16.3.2 PPGD Operation Mode Control Register (PPGCD)

      310
    • 16.3.3 PPGC/D Count Clock Select Register (PPGCD)

      312
    • 16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD)

      314
  • 16.4 Interrupts of 8-/16-bit PPG Timer

    315
  • 16.5 Explanation of Operation of 8-/16-bit PPG Timer

    316
    • 16.5.1 8-bit PPG Output 2-channel Independent Operation Mode

      317
    • 16.5.2 16-bit PPG Output Operation Mode

      320
    • 16.5.3 8+8-bit PPG Output Operation Mode

      323
  • 16.6 Precautions when Using 8-/16-bit PPG Timer

    326
• CHAPTER 17 DTP/EXTERNAL INTERRUPTS

  329
  • 17.1 Overview of DTP/External Interrupt

    330
  • 17.2 Block Diagram of DTP/External Interrupt

    331
  • 17.3 Configuration of DTP/External Interrupt

    333
    • 17.3.1 DTP/External Interrupt Factor Register (EIRR1)

      335
    • 17.3.2 DTP/External Interrupt Enable Register (ENIR1)

      337
    • 17.3.3 Detection Level Setting Register (ELVR1)

      339
    • 17.3.4 External Interrupt Factor Select Register (EISSR)

      341
  • 17.4 Explanation of Operation of DTP/External Interrupt

    343
    • 17.4.1 External Interrupt Function

      347
    • 17.4.2 DTP Function

      348
  • 17.5 Precautions when Using DTP/External Interrupt

    349
  • 17.6 Program Example of DTP/External Interrupt Function

    351
• CHAPTER 18 8-/10-BIT A/D CONVERTER

  355
  • 18.1 Overview of 8-/10-bit A/D Converter

    356
  • 18.2 Block Diagram of 8-/10-bit A/D Converter

    357
  • 18.3 Configuration of 8-/10-bit A/D Converter

    360
    • 18.3.1 A/D Control Status Register (High) (ADCS1)

      362
    • 18.3.2 A/D Control Status Register (Low) (ADCS0)

      365
    • 18.3.3 A/D Data Register (ADCR0/ADCR1)

      367
    • 18.3.4 A/D Setting Register (ADSR0/ADSR1)

      368
    • 18.3.5 Analog Input Enable Register (ADER5, ADER6)

      372
  • 18.4 Interrupt of 8-/10-bit A/D Converter

    374
  • 18.5 Explanation of Operation of 8-/10-bit A/D Converter

    375
    • 18.5.1 Single-shot Conversion Mode

      376
    • 18.5.2 Continuous Conversion Mode

      378
    • 18.5.3 Pause-conversion Mode

      380
    • 18.5.4 Conversion Using EI2OS Function

      382
    • 18.5.5 A/D-converted Data Protection Function

      383
  • 18.6 Precautions when Using 8-/10-bit A/D Converter

    385
• CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET

  387
  • 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit

    388
  • 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit

    390
  • 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register

    392
  • 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit

    394
  • 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit

    395
  • 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit

    396
• CHAPTER 20 LIN-UART

  397
  • 20.1 Overview of LIN-UART

    398
  • 20.2 Configuration of LIN-UART

    402
  • 20.3 LIN-UART Pins

    407
  • 20.4 LIN-UART Registers

    408
    • 20.4.1 Serial Control Register (SCR)

      409
    • 20.4.2 LIN-UART Serial Mode Register (SMR)

      411
    • 20.4.3 Serial Status Register (SSR)

      413
    • 20.4.4 Reception and Transmission Data Register (RDR/TDR)

      415
    • 20.4.5 Extended Status/Control Register (ESCR)

      417
    • 20.4.6 Extended Communication Control Register (ECCR)

      419
    • 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1)

      421
  • 20.5 LIN-UART Interrupts

    422
    • 20.5.1 Reception Interrupt Generation and Flag Set Timing

      425
    • 20.5.2 Transmission Interrupt Generation and Flag Set Timing

      427
  • 20.6 LIN-UART Baud Rates

    429
    • 20.6.1 Setting the Baud Rate

      431
    • 20.6.2 Restarting the Reload Counter

      434
  • 20.7 Operation of LIN-UART

    436
    • 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)

      438
    • 20.7.2 Operation in Synchronous Mode (Operation Mode 2)

      442
    • 20.7.3 Operation with LIN Function (Operation Mode 3)

      445
    • 20.7.4 Direct Access to Serial Pins

      448
    • 20.7.5 Bidirectional Communication Function (Normal Mode)

      449
    • 20.7.6 Master-Slave Communication Function (Multiprocessor Mode)

      451
    • 20.7.7 LIN Communication Function

      454
    • 20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3)

      455
  • 20.8 Notes on Using LIN-UART

    457
• CHAPTER 21 CAN CONTROLLER

  459
  • 21.1 Features of CAN Controller

    460
  • 21.2 Block Diagram of CAN Controller

    461
  • 21.3 List of Overall Control Registers

    462
  • 21.4 Classifying CAN Controller Registers

    468
    • 21.4.1 Configuration of Control Status Register (CSR)

      469
    • 21.4.2 Function of Control Status Register (CSR)

      470
    • 21.4.3 Correspondence between Node Status Bit and Node Status

      472
    • 21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)

      473
    • 21.4.5 Last Event Indicator Register (LEIR)

      474
    • 21.4.6 Receive and Transmit Error Counters (RTEC)

      477
    • 21.4.7 Bit Timing Register (BTR)

      478
    • 21.4.8 Prescaler Setting by Bit Timing Register (BTR)

      479
    • 21.4.9 Message Buffer Valid Register (BVALR)

      481
    • 21.4.10 IDE Register (IDER)

      482
    • 21.4.11 Transmission Request Register (TREQR)

      483
    • 21.4.12 Transmission RTR Register (TRTRR)

      484
    • 21.4.13 Remote Frame Receiving Wait Register (RFWTR)

      485
    • 21.4.14 Transmission Cancel Register (TCANR)

      486
    • 21.4.15 Transmission Complete Register (TCR)

      487
    • 21.4.16 Transmission Interrupt Enable Register (TIER)

      488
    • 21.4.17 Reception Complete Register (RCR)

      489
    • 21.4.18 Remote Request Receiving Register (RRTRR)

      490
    • 21.4.19 Receive Overrun Register (ROVRR)

      491
    • 21.4.20 Reception Interrupt Enable Register (RIER)

      492
    • 21.4.21 Acceptance Mask Select Register (AMSR)

      493
    • 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)

      495
    • 21.4.23 Message Buffers

      497
    • 21.4.24 ID Register x (x = 0 to 15) (IDRx)

      499
    • 21.4.25 DLC Register x (x = 0 to 15) (DLCRx)

      501
    • 21.4.26 Data Register x (x = 0 to 15) (DTRx)

      502
  • 21.5 Transmission of CAN Controller

    504
  • 21.6 Reception of CAN Controller

    506
  • 21.7 Reception Flowchart of CAN Controller

    509
  • 21.8 How to Use CAN Controller

    510
  • 21.9 Procedure for Transmission by Message Buffer (x)

    512
  • 21.10 Procedure for Reception by Message Buffer (x)

    514
  • 21.11 Setting Configuration of Multi-level Message Buffer

    516
  • 21.12 Setting the CAN Direct Mode Register

    518
  • 21.13 Precautions when Using CAN Controller

    519
• CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION

  521
  • 22.1 Overview of Address Match Detection Function

    522
  • 22.2 Block Diagram of Address Match Detection Function

    523
  • 22.3 Configuration of Address Match Detection Function

    524
    • 22.3.1 Address Detection Control Register (PACSR0/PACSR1)

      525
    • 22.3.2 Detect Address Setting Registers (PADR0 to PADR5)

      529
  • 22.4 Explanation of Operation of Address Match Detection Function

    532
    • 22.4.1 Example of using Address Match Detection Function

      533
  • 22.5 Program Example of Address Match Detection Function

    538
• CHAPTER 23 ROM MIRRORING MODULE

  541
  • 23.1 Overview of ROM Mirroring Function Select Module

    542
  • 23.2 ROM Mirroring Function Select Register (ROMM)

    544
• CHAPTER 24 512K-BIT FLASH MEMORY

  545
  • 24.1 Overview of 512K-bit Flash Memory

    546
  • 24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory

    547
  • 24.3 Write/Erase Modes

    549
  • 24.4 Flash Memory Control Status Register (FMCS)

    551
  • 24.5 Starting the Flash Memory Automatic Algorithm

    554
  • 24.6 Confirming the Automatic Algorithm Execution State

    555
    • 24.6.1 Data Polling Flag (DQ7)

      557
    • 24.6.2 Toggle Bit Flag (DQ6)

      558
    • 24.6.3 Timing Limit Exceeded Flag (DQ5)

      559
  • 24.7 Detailed Explanation of Writing to and Erasing Flash Memory

    560
    • 24.7.1 Setting The Read/Reset State

      561
    • 24.7.2 Writing Data

      562
    • 24.7.3 Erasing All Data (Erasing Chips)

      564
  • 24.8 Notes on Using 512K-bit Flash Memory

    566
  • 24.9 Flash Security Feature

    567
• CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION

  569
  • 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S)

    570
  • 25.2 Example of Serial Programming Connection (User Power Supply Used)

    573
  • 25.3 Example of Serial Programming Connection (Power Supplied from Programmer)

    575
  • 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)

    577
  • 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)

    579
• CHAPTER 26 ROM SECURITY FUNCTION

  581
  • 26.1 Overview of ROM Security Function

    582
• APPENDIX

  583
  • APPENDIX A I/O Maps

    584
  • APPENDIX B Instructions

    592
    • B.1 Instruction Types

      593
    • B.2 Addressing

      594
    • B.3 Direct Addressing

      596
    • B.4 Indirect Addressing

      602
    • B.5 Execution Cycle Count

      609
    • B.6 Effective address field

      612
    • B.7 How to Read the Instruction List

      613
    • B.8 F2MC-16LX Instruction List

      616
    • B.9 Instruction Map

      630
  • APPENDIX C Timing Diagrams in Flash Memory Mode

    652
  • APPENDIX D List of Interrupt Vectors

    660