用户手册目录CHAPTER 1 OVERVIEW171.1 Overview of MB90360181.2 Block Diagram of MB90360 series251.3 Package Dimensions281.4 Pin Assignment291.5 Pin Functions301.6 Input-Output Circuits331.7 Handling Device37CHAPTER 2 CPU432.1 Outline of the CPU442.2 Memory Space452.3 Memory Map482.4 Linear Addressing492.5 Bank Addressing Types502.6 Multi-byte Data in Memory Space522.7 Registers532.7.1 Accumulator (A)562.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP)572.7.3 Processor Status (PS)582.7.4 Program Counter (PC)612.8 Register Bank622.9 Prefix Codes642.10 Interrupt Disable Instructions672.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions68CHAPTER 3 INTERRUPTS713.1 Outline of Interrupts723.2 Interrupt Vector753.3 Interrupt Control Registers (ICR)773.4 Interrupt Flow813.5 Hardware Interrupts833.5.1 Hardware Interrupt Operation843.5.2 Occurrence and Release of Hardware Interrupt853.5.3 Multiple interrupts873.6 Software Interrupts883.7 Extended Intelligent I/O Service (EI2OS)903.7.1 Extended Intelligent I/O Service Descriptor (ISD)923.7.2 EI2OS Status Register (ISCS)943.8 Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI2OS)953.9 Exceptions98CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE994.1 Overview of Delayed Interrupt Generation Module1004.2 Block Diagram of Delayed Interrupt Generation Module1014.3 Configuration of Delayed Interrupt Generation Module1024.3.1 Delayed interrupt request generate/cancel register (DIRR)1034.4 Explanation of Operation of Delayed Interrupt Generation Module1044.5 Precautions when Using Delayed Interrupt Generation Module1054.6 Program Example of Delayed Interrupt Generation Module106CHAPTER 5 CLOCKS1075.1 Clocks1085.2 Block Diagram of the Clock Generation Block1115.2.1 Register of Clock Generation Block1135.3 Clock Selection Register (CKSCR)1145.4 PLL/Subclock Control Register (PSCCR)1175.5 Clock Mode1195.6 Oscillation Stabilization Wait Interval1235.7 Connection of an Oscillator or an External Clock to the Microcontroller124CHAPTER 6 CLOCK SUPERVISOR1256.1 Overview of Clock Supervisor1266.2 Block Diagram of Clock Supervisor1276.3 Clock Supervisor Control Register (CSVCR)1296.4 Operating Mode of Clock Supervisor131CHAPTER 7 RESETS1357.1 Resets1367.2 Reset Cause and Oscillation Stabilization Wait Times1397.3 External Reset Pin1417.4 Reset Operation1427.5 Reset Cause Bits1447.6 Status of Pins in a Reset148CHAPTER 8 LOW-POWER CONSUMPTION MODE1498.1 Overview of Low-Power Consumption Mode1508.2 Block Diagram of the Low-Power Consumption Control Circuit1538.3 Low-Power Consumption Mode Control Register (LPMCR)1558.4 CPU Intermittent Operation Mode1588.5 Standby Mode1598.5.1 Sleep Mode1618.5.2 Watch Mode1648.5.3 Timebase Timer Mode1668.5.4 Stop Mode1688.6 Status Change Diagram1718.7 Status of Pins in Standby Mode and during Hold and Reset1728.8 Usage Notes on Low-Power Consumption Mode173CHAPTER 9 MEMORY ACCESS MODES1779.1 Outline of Memory Access Modes1789.1.1 Mode Pins1799.1.2 Mode Data1809.1.3 Memory Space in Each Bus Mode181CHAPTER 10 I/O PORTS18310.1 I/O Ports18410.2 I/O Port Registers18510.2.1 Port Data Register (PDR)18610.2.2 Port Direction Register (DDR)18810.2.3 Pull-up Control Register (PUCR)19010.2.4 Analog Input Enable Register (ADER)19110.2.5 Input Level Select Register192CHAPTER 11 TIMEBASE TIMER19511.1 Overview of Timebase Timer19611.2 Block Diagram of Timebase Timer19811.3 Configuration of Timebase Timer20011.3.1 Timebase timer control register (TBTC)20111.4 Interrupt of Timebase Timer20311.5 Explanation of Operations of Timebase Timer Functions20411.6 Precautions when Using Timebase Timer20811.7 Program Example of Timebase Timer209CHAPTER 12 WATCHDOG TIMER21112.1 Overview of Watchdog Timer21212.2 Configuration of Watchdog Timer21512.3 Watchdog Timer Registers21712.3.1 Watchdog timer control register (WDTC)21812.4 Explanation of Operations of Watchdog Timer Functions22012.5 Precautions when Using Watchdog Timer22312.6 Program Examples of Watchdog Timer224CHAPTER 13 16-Bit I/O TIMER22513.1 Overview of 16-bit I/O Timer22613.2 Block Diagram of 16-bit I/O Timer22713.2.1 Block Diagram of 16-bit Free-run Timer22913.2.2 Block Diagram of Input Capture23013.3 Configuration of 16-bit I/O Timer23213.3.1 Timer Control Status Register (Upper) (TCCSH)23313.3.2 Timer Control Status Register (Lower) (TCCSL)23413.3.3 Timer Data Register (TCDT)23613.3.4 Input Capture Control Status Registers (ICS)23713.3.5 Input Capture Register (IPCP)23913.3.6 Input Capture Edge Register (ICE)24013.4 Interrupts of 16-bit I/O Timer24313.5 Explanation of Operation of 16-bit Free-run Timer24513.6 Explanation of Operation of Input Capture24713.7 Precautions when Using 16-bit I/O Timer24913.8 Program Example of 16-bit I/O Timer250CHAPTER 14 16-BIT RELOAD TIMER25314.1 Overview of the 16-bit Reload Timer25414.2 Block Diagram of 16-bit Reload Timer25614.3 Configuration of 16-bit Reload Timer25814.3.1 Timer Control Status Registers (High) (TMCSR:H)26114.3.2 Timer Control Status Registers (Low) (TMCSR: L)26314.3.3 16-bit Timer Registers (TMR)26514.3.4 16-bit Reload Registers (TMRLR)26614.4 Interrupts of 16-bit Reload Timer26714.5 Explanation of Operation of 16-bit Reload Timer26814.5.1 Operation in Internal Clock Mode27014.5.2 Operation in Event Count Mode27514.6 Precautions when Using 16-bit Reload Timer27814.7 Sample Program of 16-bit Reload Timer279CHAPTER 15 WATCH TIMER28315.1 Overview of Watch Timer28415.2 Block Diagram of Watch Timer28615.3 Configuration of Watch Timer28815.3.1 Watch Timer Control Register (WTC)28915.4 Watch Timer Interrupt29115.5 Explanation of Operation of Watch Timer29215.6 Program Example of Watch Timer294CHAPTER 16 8-/16-BIT PPG TIMER29716.1 Overview of 8-/16-bit PPG Timer29816.2 Block Diagram of 8-/16-bit PPG Timer30116.2.1 Block Diagram for 8-/16-bit PPG Timer C30216.2.2 Block Diagram of 8-/16-bit PPG Timer D30416.3 Configuration of 8-/16-bit PPG Timer30616.3.1 PPGC Operation Mode Control Register (PPGCC)30816.3.2 PPGD Operation Mode Control Register (PPGCD)31016.3.3 PPGC/D Count Clock Select Register (PPGCD)31216.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD)31416.4 Interrupts of 8-/16-bit PPG Timer31516.5 Explanation of Operation of 8-/16-bit PPG Timer31616.5.1 8-bit PPG Output 2-channel Independent Operation Mode31716.5.2 16-bit PPG Output Operation Mode32016.5.3 8+8-bit PPG Output Operation Mode32316.6 Precautions when Using 8-/16-bit PPG Timer326CHAPTER 17 DTP/EXTERNAL INTERRUPTS32917.1 Overview of DTP/External Interrupt33017.2 Block Diagram of DTP/External Interrupt33117.3 Configuration of DTP/External Interrupt33317.3.1 DTP/External Interrupt Factor Register (EIRR1)33517.3.2 DTP/External Interrupt Enable Register (ENIR1)33717.3.3 Detection Level Setting Register (ELVR1)33917.3.4 External Interrupt Factor Select Register (EISSR)34117.4 Explanation of Operation of DTP/External Interrupt34317.4.1 External Interrupt Function34717.4.2 DTP Function34817.5 Precautions when Using DTP/External Interrupt34917.6 Program Example of DTP/External Interrupt Function351CHAPTER 18 8-/10-BIT A/D CONVERTER35518.1 Overview of 8-/10-bit A/D Converter35618.2 Block Diagram of 8-/10-bit A/D Converter35718.3 Configuration of 8-/10-bit A/D Converter36018.3.1 A/D Control Status Register (High) (ADCS1)36218.3.2 A/D Control Status Register (Low) (ADCS0)36518.3.3 A/D Data Register (ADCR0/ADCR1)36718.3.4 A/D Setting Register (ADSR0/ADSR1)36818.3.5 Analog Input Enable Register (ADER5, ADER6)37218.4 Interrupt of 8-/10-bit A/D Converter37418.5 Explanation of Operation of 8-/10-bit A/D Converter37518.5.1 Single-shot Conversion Mode37618.5.2 Continuous Conversion Mode37818.5.3 Pause-conversion Mode38018.5.4 Conversion Using EI2OS Function38218.5.5 A/D-converted Data Protection Function38318.6 Precautions when Using 8-/10-bit A/D Converter385CHAPTER 19 LOW VOLTAGE DETECTION/ CPU OPERATING DETECTION RESET38719.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit38819.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit39019.3 Low Voltage/CPU Operating Detection Reset Circuit Register39219.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit39419.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit39519.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit396CHAPTER 20 LIN-UART39720.1 Overview of LIN-UART39820.2 Configuration of LIN-UART40220.3 LIN-UART Pins40720.4 LIN-UART Registers40820.4.1 Serial Control Register (SCR)40920.4.2 LIN-UART Serial Mode Register (SMR)41120.4.3 Serial Status Register (SSR)41320.4.4 Reception and Transmission Data Register (RDR/TDR)41520.4.5 Extended Status/Control Register (ESCR)41720.4.6 Extended Communication Control Register (ECCR)41920.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1)42120.5 LIN-UART Interrupts42220.5.1 Reception Interrupt Generation and Flag Set Timing42520.5.2 Transmission Interrupt Generation and Flag Set Timing42720.6 LIN-UART Baud Rates42920.6.1 Setting the Baud Rate43120.6.2 Restarting the Reload Counter43420.7 Operation of LIN-UART43620.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1)43820.7.2 Operation in Synchronous Mode (Operation Mode 2)44220.7.3 Operation with LIN Function (Operation Mode 3)44520.7.4 Direct Access to Serial Pins44820.7.5 Bidirectional Communication Function (Normal Mode)44920.7.6 Master-Slave Communication Function (Multiprocessor Mode)45120.7.7 LIN Communication Function45420.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3)45520.8 Notes on Using LIN-UART457CHAPTER 21 CAN CONTROLLER45921.1 Features of CAN Controller46021.2 Block Diagram of CAN Controller46121.3 List of Overall Control Registers46221.4 Classifying CAN Controller Registers46821.4.1 Configuration of Control Status Register (CSR)46921.4.2 Function of Control Status Register (CSR)47021.4.3 Correspondence between Node Status Bit and Node Status47221.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1)47321.4.5 Last Event Indicator Register (LEIR)47421.4.6 Receive and Transmit Error Counters (RTEC)47721.4.7 Bit Timing Register (BTR)47821.4.8 Prescaler Setting by Bit Timing Register (BTR)47921.4.9 Message Buffer Valid Register (BVALR)48121.4.10 IDE Register (IDER)48221.4.11 Transmission Request Register (TREQR)48321.4.12 Transmission RTR Register (TRTRR)48421.4.13 Remote Frame Receiving Wait Register (RFWTR)48521.4.14 Transmission Cancel Register (TCANR)48621.4.15 Transmission Complete Register (TCR)48721.4.16 Transmission Interrupt Enable Register (TIER)48821.4.17 Reception Complete Register (RCR)48921.4.18 Remote Request Receiving Register (RRTRR)49021.4.19 Receive Overrun Register (ROVRR)49121.4.20 Reception Interrupt Enable Register (RIER)49221.4.21 Acceptance Mask Select Register (AMSR)49321.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1)49521.4.23 Message Buffers49721.4.24 ID Register x (x = 0 to 15) (IDRx)49921.4.25 DLC Register x (x = 0 to 15) (DLCRx)50121.4.26 Data Register x (x = 0 to 15) (DTRx)50221.5 Transmission of CAN Controller50421.6 Reception of CAN Controller50621.7 Reception Flowchart of CAN Controller50921.8 How to Use CAN Controller51021.9 Procedure for Transmission by Message Buffer (x)51221.10 Procedure for Reception by Message Buffer (x)51421.11 Setting Configuration of Multi-level Message Buffer51621.12 Setting the CAN Direct Mode Register51821.13 Precautions when Using CAN Controller519CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION52122.1 Overview of Address Match Detection Function52222.2 Block Diagram of Address Match Detection Function52322.3 Configuration of Address Match Detection Function52422.3.1 Address Detection Control Register (PACSR0/PACSR1)52522.3.2 Detect Address Setting Registers (PADR0 to PADR5)52922.4 Explanation of Operation of Address Match Detection Function53222.4.1 Example of using Address Match Detection Function53322.5 Program Example of Address Match Detection Function538CHAPTER 23 ROM MIRRORING MODULE54123.1 Overview of ROM Mirroring Function Select Module54223.2 ROM Mirroring Function Select Register (ROMM)544CHAPTER 24 512K-BIT FLASH MEMORY54524.1 Overview of 512K-bit Flash Memory54624.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory54724.3 Write/Erase Modes54924.4 Flash Memory Control Status Register (FMCS)55124.5 Starting the Flash Memory Automatic Algorithm55424.6 Confirming the Automatic Algorithm Execution State55524.6.1 Data Polling Flag (DQ7)55724.6.2 Toggle Bit Flag (DQ6)55824.6.3 Timing Limit Exceeded Flag (DQ5)55924.7 Detailed Explanation of Writing to and Erasing Flash Memory56024.7.1 Setting The Read/Reset State56124.7.2 Writing Data56224.7.3 Erasing All Data (Erasing Chips)56424.8 Notes on Using 512K-bit Flash Memory56624.9 Flash Security Feature567CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION56925.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S)57025.2 Example of Serial Programming Connection (User Power Supply Used)57325.3 Example of Serial Programming Connection (Power Supplied from Programmer)57525.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used)57725.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer)579CHAPTER 26 ROM SECURITY FUNCTION58126.1 Overview of ROM Security Function582APPENDIX583APPENDIX A I/O Maps584APPENDIX B Instructions592B.1 Instruction Types593B.2 Addressing594B.3 Direct Addressing596B.4 Indirect Addressing602B.5 Execution Cycle Count609B.6 Effective address field612B.7 How to Read the Instruction List613B.8 F2MC-16LX Instruction List616B.9 Instruction Map630APPENDIX C Timing Diagrams in Flash Memory Mode652APPENDIX D List of Interrupt Vectors660文件大小： 12.7 MB页数： 682Language: English打开用户手册
