Manuais de utilizador para Intel 2 Duo E8200

índice analítico

• Intel® Core™2 Duo Processor E8000D Series

  1
  • Contents

    3
    • Figures

      5
    • Tables

      6
  • Intel® Core™2 Duo Processor E8000 Series Features

    7
  • Revision History

    8
• 1 Introduction

  9
  • 1.1 Terminology

    9
    • 1.1.1 Processor Terminology Definitions

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  • 1.2 References

    11
    • Table 1. References

      11
• 2 Electrical Specifications

  13
  • 2.1 Power and Ground Lands

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  • 2.2 Decoupling Guidelines

    13
    • 2.2.1 VCC Decoupling

      13
    • 2.2.2 VTT Decoupling

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    • 2.2.3 FSB Decoupling

      14
  • 2.3 Voltage Identification

    14
    • Table 2. Voltage Identification Definition

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  • 2.4 Reserved, Unused, and TESTHI Signals

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  • 2.5 Power Segment Identifier (PSID)

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  • 2.6 Voltage and Current Specification

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    • 2.6.1 Absolute Maximum and Minimum Ratings

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      • Table 3. Absolute Maximum and Minimum Ratings

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    • 2.6.2 DC Voltage and Current Specification

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      • Table 4. Voltage and Current Specifications

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      • Table 5. Processor VCC Static and Transient Tolerance

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      • Figure 1. Processor VCC Static and Transient Tolerance

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    • 2.6.3 VCC Overshoot

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      • Table 6. VCC Overshoot Specifications

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      • Figure 2. VCC Overshoot Example Waveform

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    • 2.6.4 Die Voltage Validation

      22
  • 2.7 Signaling Specifications

    22
    • 2.7.1 FSB Signal Groups

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      • Table 7. FSB Signal Groups

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      • Table 8. Signal Characteristics

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      • Table 9. Signal Reference Voltages

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    • 2.7.2 CMOS and Open Drain Signals

      24
    • 2.7.3 Processor DC Specifications

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      • Table 10. GTL+ Signal Group DC Specifications

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      • Table 11. Open Drain and TAP Output Signal Group DC Specifications

        25
      • Table 12. CMOS Signal Group DC Specifications

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      • 2.7.3.1 Platform Environment Control Interface (PECI) DC Specifications

        26
        • Table 13. PECI DC Electrical Limits

          27
      • 2.7.3.2 GTL+ Front Side Bus Specifications

        27
        • Table 14. GTL+ Bus Voltage Definitions

          28
  • 2.8 Clock Specifications

    28
    • 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

      28
      • Table 15. Core Frequency to FSB Multiplier Configuration

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    • 2.8.2 FSB Frequency Select Signals (BSEL[2:0])

      29
      • Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]

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    • 2.8.3 Phase Lock Loop (PLL) and Filter

      30
    • 2.8.4 BCLK[1:0] Specifications

      30
      • Table 17. Front Side Bus Differential BCLK Specifications

        30
      • Table 18. FSB Differential Clock Specifications (1333 MHz FSB)

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      • Figure 3. Differential Clock Waveform

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      • Figure 4. Measurement Points for Differential Clock Waveforms

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• 3 Package Mechanical Specifications

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  • Figure 5. Processor Package Assembly Sketch

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  • 3.0.1 Package Mechanical Drawing

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    • Figure 6. Processor Package Drawing Sheet 1 of 3

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    • Figure 7. Processor Package Drawing Sheet 2 of 3

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    • Figure 8. Processor Package Drawing Sheet 3 of 3

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  • 3.0.2 Processor Component Keep-Out Zones

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  • 3.0.3 Package Loading Specifications

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    • Table 19. Processor Loading Specifications

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  • 3.0.4 Package Handling Guidelines

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    • Table 20. Package Handling Guidelines

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  • 3.0.5 Package Insertion Specifications

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  • 3.0.6 Processor Mass Specification

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  • 3.0.7 Processor Materials

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    • Table 21. Processor Materials

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  • 3.0.8 Processor Markings

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    • Figure 9. Processor Top-Side Markings Example

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  • 3.0.9 Processor Land Coordinates

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    • Figure 10. Processor Land Coordinates and Quadrants, Top View

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• 4 Land Listing and Signal Descriptions

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  • 4.1 Processor Land Assignments

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    • Figure 11. land-out Diagram (Top View - Left Side)

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    • Figure 12. land-out Diagram (Top View - Right Side)

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    • Table 22. Alphabetical Land Assignments

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    • Table 23. Numerical Land Assignment

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  • 4.2 Alphabetical Signals Reference

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    • Table 24. Signal Description (Sheet 1 of 10)

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• 5 Thermal Specifications and Design Considerations

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  • 5.1 Processor Thermal Specifications

    75
    • 5.1.1 Thermal Specifications

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      • Table 25. Processor Thermal Specifications

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      • Table 26. Processor Thermal Profile

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      • Figure 13. Processor Thermal Profile

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    • 5.1.2 Thermal Metrology

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      • Figure 14. Case Temperature (TC) Measurement Location

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  • 5.2 Processor Thermal Features

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    • 5.2.1 Thermal Monitor

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    • 5.2.2 Thermal Monitor 2

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      • Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering

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    • 5.2.3 On-Demand Mode

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    • 5.2.4 PROCHOT# Signal

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    • 5.2.5 THERMTRIP# Signal

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  • 5.3 Platform Environment Control Interface (PECI)

    81
    • 5.3.1 Introduction

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      • 5.3.1.1 TCONTROL and TCC activation on PECI-Based Systems

        82
        • Figure 16. Conceptual Fan Control Diagram on PECI-Based Platforms

          82
    • 5.3.2 PECI Specifications

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      • 5.3.2.1 PECI Device Address

        82
      • 5.3.2.2 PECI Command Support

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      • 5.3.2.3 PECI Fault Handling Requirements

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      • 5.3.2.4 PECI GetTemp0() Error Code Support

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        • Table 27. GetTemp0() Error Codes

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• 6 Features

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  • 6.1 Power-On Configuration Options

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    • Table 28. Power-On Configuration Option Signals

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  • 6.2 Clock Control and Low Power States

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    • Figure 17. Processor Low Power State Machine

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    • 6.2.1 Normal State

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    • 6.2.2 HALT and Extended HALT Powerdown States

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      • 6.2.2.1 HALT Powerdown State

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      • 6.2.2.2 Extended HALT Powerdown State

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    • 6.2.3 Stop Grant and Extended Stop Grant States

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      • 6.2.3.1 Stop-Grant State

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      • 6.2.3.2 Extended Stop Grant State

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    • 6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State

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      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

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      • 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State

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    • 6.2.5 Sleep State

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    • 6.2.6 Deep Sleep State

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    • 6.2.7 Deeper Sleep State

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    • 6.2.8 Enhanced Intel SpeedStep® Technology

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• 7 Boxed Processor Specifications

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  • 7.1 Introduction

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    • Figure 18. Mechanical Representation of the Boxed Processor

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  • 7.2 Mechanical Specifications

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    • 7.2.1 Boxed Processor Cooling Solution Dimensions

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      • Figure 19. Space Requirements for the Boxed Processor (Side View)

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      • Figure 20. Space Requirements for the Boxed Processor (Top View)

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      • Figure 21. Overall View Space Requirements for the Boxed Processor

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    • 7.2.2 Boxed Processor Fan Heatsink Weight

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    • 7.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

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  • 7.3 Electrical Requirements

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    • 7.3.1 Fan Heatsink Power Supply

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      • Figure 22. Boxed Processor Fan Heatsink Power Cable Connector Description

        94
      • Table 29. Fan Heatsink Power and Signal Specifications

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      • Figure 23. Baseboard Power Header Placement Relative to Processor Socket

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  • 7.4 Thermal Specifications

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    • 7.4.1 Boxed Processor Cooling Requirements

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      • Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

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      • Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)

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    • 7.4.2 Variable Speed Fan

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      • Figure 26. Boxed Processor Fan Heatsink Set Points

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      • Table 30. Fan Heatsink Power and Signal Specifications

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• 8 Debug Tools Specifications

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  • 8.1 Logic Analyzer Interface (LAI)

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    • 8.1.1 Mechanical Considerations

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    • 8.1.2 Electrical Considerations

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