Manual Do Utilizador (AU80610006252AA)índice analíticoI21 Processor Configuration Registers81.1 Register Terminology81.2 System Address Map101.2.1 Legacy Address Range121.2.2 Main Memory Address Range (1 MB - TOLUD)151.2.3 PCI* Memory Address Range (TOLUD - 4 GB)181.2.4 Main Memory Address Space (4 GB to TOUUD)201.2.5 PCI Express Configuration Address Space211.2.6 Graphics Memory Address Ranges221.2.7 System Management Mode (SMM)221.2.8 Memory Shadowing251.2.9 I/O Address Space251.2.10 Memory Controller Decode Rules and Cross-Bridge Address Mapping261.3 Processor Register Introduction261.4 I/O Mapped Registers271.5 PCI Device 0281.5.1 VID - Vendor Identification301.5.2 DID - Device Identification311.5.3 PCICMD - PCI Command311.5.4 PCISTS - PCI Status331.5.5 RID - Revision Identification351.5.6 CC - Class Code351.5.7 MLT - Master Latency Timer361.5.8 HDR - Header Type361.5.9 SVID - Subsystem Vendor Identification361.5.10 SID - Subsystem Identification371.5.11 CAPPTR - Capabilities Pointer371.5.12 PXPEPBAR - PCI Express Egress Port Base Address371.5.13 MCHBAR - GMCH Memory Mapped Register Range Base381.5.14 GGC - GMCH Graphics Control Register391.5.15 DEVEN - Device Enable411.5.16 PCIEXBAR - PCI Express Register Range Base Address421.5.17 DMIBAR - Root Complex Register Range Base Address441.5.18 PAM0 - Programmable Attribute Map 0441.5.19 PAM1 - Programmable Attribute Map 1461.5.20 PAM2 - Programmable Attribute Map 2471.5.21 PAM3 - Programmable Attribute Map 3481.5.22 PAM4 - Programmable Attribute Map 4491.5.23 PAM5 - Programmable Attribute Map 5501.5.24 PAM6 - Programmable Attribute Map 6511.5.25 LAC - Legacy Access Control521.5.26 REMAPBASE - Remap Base Address Register521.5.27 REMAPLIMIT - Remap Limit Address Register531.5.28 SMRAM - System Management RAM Control531.5.29 ESMRAMC - Extended System Management RAM Control551.5.30 TOM - Top of Memory561.5.31 TOUUD - Top of Upper Usable Dram571.5.32 GBSM - Graphics Base of Stolen Memory571.5.33 BGSM - Base of GTT stolen Memory581.5.34 TSEGMB - TSEG Memory Base591.5.35 TOLUD - Top of Low Usable DRAM591.5.36 ERRSTS - Error Status611.5.37 ERRCMD - Error Command621.5.38 SMICMD - SMI Command631.5.39 SKPD - Scratchpad Data641.5.40 CAPID0 - Capability Identifier641.6 MCHBAR661.6.1 CHDECMISC - Channel Decode Misc671.6.2 C0DRB0 - Channel 0 DRAM Rank Boundary Address 0681.6.3 C0DRB1 - Channel 0 DRAM Rank Boundary Address 1691.6.4 C0DRB2 - Channel 0 DRAM Rank Boundary Address 2691.6.5 C0DRB3 - Channel 0 DRAM Rank Boundary Address 3701.6.6 C0DRA01 - Channel 0 DRAM Rank 0,1 Attribute701.6.7 C0DRA23 - Channel 0 DRAM Rank 2, 3 Attribute721.6.8 C0CYCTRKPCHG - Channel 0 CYCTRK PCHG721.6.9 C0CYCTRKACT - Channel 0 CYCTRK ACT731.6.10 C0CYCTRKWR - Channel 0 CYCTRK WR741.6.11 C0CYCTRKRD - Channel 0 CYCTRK READ751.6.12 C0CYCTRKREFR - Channel 0 CYCTRK REFR761.6.13 C0CKECTRL - Channel 0 CKE Control761.6.14 C0REFRCTRL - Channel 0 DRAM Refresh Control781.6.15 C0ODTCTRL - Channel 0 ODT Control801.6.16 PMSTS - Power Management Status811.7 DMIBAR821.7.1 DMIVCECH - DMI Virtual Channel Enhanced Capability831.7.2 DMIPVCCAP1 - DMI Port VC Capability Register 1841.7.3 DMIPVCCAP2 - DMI Port VC Capability Register 2851.7.4 DMIPVCCTL - DMI Port VC Control851.7.5 DMIVC0RCAP - DMI VC0 Resource Capability861.7.6 DMIVC0RCTL0 - DMI VC0 Resource Control861.7.7 DMIVC0RSTS - DMI VC0 Resource Status871.7.8 DMIVC1RCAP - DMI VC1 Resource Capability881.7.9 DMIVC1RCTL1 - DMI VC1 Resource Control891.7.10 DMIVC1RSTS - DMI VC1 Resource Status901.7.11 DMIRCLDECH - DMI Root Complex Link Declaration911.7.12 DMIESD - DMI Element Self Description911.7.13 DMILE1D - DMI Link Entry 1 Description921.7.14 DMILE1A - DMI Link Entry 1 Address931.7.15 DMILE2D - DMI Link Entry 2 Description941.7.16 DMILE2A - DMI Link Entry 2 Address951.7.17 DMIRCILCECH - DMI Root Complex Internal Link Control951.7.18 DMILCAP - DMI Link Capabilities961.7.19 DMILCTL - DMI Link Control971.7.20 DMILSTS - DMI Link Status981.8 EPBAR981.8.1 EPESD - EP Element Self Description991.8.2 EPLE1D - EP Link Entry 1 Description1001.8.3 EPLE1A - EP Link Entry 1 Address1011.8.4 EPLE2D - EP Link Entry 2 Description1011.8.5 EPLE2A - EP Link Entry 2 Address1021.9 PCI Device 2 Function 01021.9.1 VID2 - Vendor Identification1051.9.2 DID - Device Identification1051.9.3 PCICMD2 - PCI Command1061.9.4 PCISTS2 - PCI Status1071.9.5 RID2 - Revision Identification1081.9.6 CC - Class Code1091.9.7 CLS - Cache Line Size1091.9.8 MLT2 - Master Latency Timer1101.9.9 HDR2 - Header Type1101.9.10 MMADR - Memory Mapped Range Address1101.9.11 IOBAR - I/O Base Address1111.9.12 GMADR - Graphics Memory Range Address1121.9.13 GTTADR - Graphics Translation Table Range Address1131.9.14 SVID2 - Subsystem Vendor Identification1131.9.15 SID2 - Subsystem Identification1141.9.16 ROMADR - Video BIOS ROM Base Address1141.9.17 CAPPOINT - Capabilities Pointer1151.9.18 INTRLINE - Interrupt Line1151.9.19 INTRPIN - Interrupt Pin1161.9.20 MINGNT - Minimum Grant1161.9.21 MAXLAT - Maximum Latency1161.9.22 CAPID0 - Mirror of Device 0 Capability Identifier1171.9.23 MGGC - GMCH Graphics Control Register1181.9.24 DEVEN - Device Enable1201.9.25 SSRW - Software Scratch Read Write1211.9.26 BSM - Base of Stolen Memory1211.9.27 HSRW - Hardware Scratch Read Write1221.9.28 MSAC - Multi Size Aperture Control1221.9.29 SCWBFC - Secondary CWB Flush Control1231.9.30 MSI_CAPID - Message Signaled Interrupts Capability ID1231.9.31 MC - Message Control1241.9.32 MA - Message Address1251.9.33 MD - Message Data1251.9.34 GDRST - Graphics Debug Reset1261.9.35 PMCAPID - Power Management Capabilities ID1271.9.36 PMCAP - Power Management Capabilities1271.9.37 PMCS - Power Management Control/Status1281.9.38 SWSMI - Software SMI1291.9.39 LBB - LBB-Legacy Backlight Brightness1301.10 PCI Device 2 Function 11301.10.1 VID2 - Vendor Identification1321.10.2 DID2 - Device Identification1331.10.3 PCICMD2 - PCI Command1331.10.4 PCISTS2 - PCI Status1351.10.5 RID2 - Revision Identification1361.10.6 CC - Class Code Register1371.10.7 CLS - Cache Line Size1371.10.8 MLT2 - Master Latency Timer1381.10.9 HDR2 - Header Type1381.10.10 MMADR - Memory Mapped Range Address1391.10.11 SVID2 - Subsystem Vendor Identification1391.10.12 SID2 - Subsystem Identification1401.10.13 ROMADR - Video BIOS ROM Base Address1401.10.14 CAPPOINT - Capabilities Pointer1411.10.15 MINGNT - Minimum Grant1411.10.16 MAXLAT - Maximum Latency1411.10.17 CAPID0 - Mirror of Device 0 Capability Identifier1421.10.18 MGGC - Mirror of Dev 0 GMCH Graphics Control Register1431.10.19 DEVEN - Device Enable1451.10.20 SSRW - Mirror of Fun 0 Software Scratch Read Write1461.10.21 BSM - Mirror of Func0 Base of Stolen Memory1461.10.22 HSRW - Mirror of Dev2 Func0 Hardware Scratch Read Write1471.10.23 MSAC - Mirror of Dev2 Func0 Multi Size Aperture Control1471.10.24 GDRST - Mirror of Dev2 Func0 Graphics Debug Reset1481.10.25 PMCAPID - Mirror of Fun 0 Power Management Capabilities ID1491.10.26 PMCAP - Mirror of Fun 0 Power Management Capabilities1491.10.27 PMCS - Power Management Control/Status1501.10.28 SWSMI - Mirror of Func0 Software SMI1511.11 Device 2 IO1521.11.1 Index - MMIO Address Register1521.11.2 Data - MMIO Data Register153Tamanho: 1000 KBPáginas: 153Language: EnglishAbrir o manual