Manuais de utilizador para Microchip Technology IC PIC MCU PIC18F65J15-I/PT TQFP-64 MCP

índice analítico

• Special Microcontroller Features:

  3
• Flexible Oscillator Structure:

  3
• Peripheral Highlights:

  3
• External Memory Bus (PIC18F8XJ10/8XJ15 only):

  3
• Pin Diagrams

  4
• Pin Diagrams (Continued)

  5
• Table of Contents

  6
• Most Current Data Sheet

  6
• Errata

  6
• Customer Notification System

  6
• 1.0 Device Overview

  7
  • 1.1 Core Features

    7
    • 1.1.1 nanoWatt Technology

      7
    • 1.1.2 Oscillator Options and Features

      7
    • 1.1.3 Expanded Memory

      7
    • 1.1.4 External Memory Bus

      7
    • 1.1.5 Extended Instruction Set

      7
    • 1.1.6 Easy Migration

      8
  • 1.2 Other Special Features

    8
  • 1.3 Details on Individual Family Members

    8
    • TABLE 1-1: Device Features for the PIC18F87J10 Family (64-pin Devices)

      9
    • TABLE 1-2: Device Features for the PIC18F87J10 Family (80-pin Devices)

      9
    • FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-pin) Block Diagram

      10
    • FIGURE 1-2: PIC18F8XJ10/8XJ15 (80-pin) Block Diagram

      11
    • TABLE 1-3: PIC18F6XJ10/6XJ15 Pinout I/O Descriptions

      12
    • TABLE 1-4: PIC18F8XJ10/8XJ15 Pinout I/O Descriptions

      19
• 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers

  29
  • 2.1 Basic Connection Requirements

    29
    • FIGURE 2-1: Recommended Minimum connections

      29
  • 2.2 Power Supply Pins

    30
    • 2.2.1 Decoupling Capacitors

      30
    • 2.2.2 Tank Capacitors

      30
  • 2.3 Master Clear (MCLR) Pin

    30
    • FIGURE 2-2: Example of MCLR Pin Connections

      30
  • 2.4 Voltage Regulator Pins (ENVREG and Vcap/Vddcore)

    31
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      31
  • 2.5 ICSP Pins

    31
  • 2.6 External Oscillator Pins

    32
    • FIGURE 2-4: Suggested Placement of the Oscillator Circuit

      32
  • 2.7 Unused I/Os

    32
• 3.0 Oscillator Configurations

  33
  • 3.1 Oscillator Types

    33
  • 3.2 Crystal Oscillator/Ceramic Resonators (HS Modes)

    33
    • FIGURE 3-1: Crystal/Ceramic Resonator Operation (HS or HSPLL Configuration)

      33
    • TABLE 3-1: Capacitor Selection for Ceramic Resonators

      33
    • TABLE 3-2: Capacitor Selection for Crystal Oscillator

      34
  • 3.3 External Clock Input (EC Modes)

    34
    • FIGURE 3-2: External Clock Input Operation (EC Configuration)

      34
    • FIGURE 3-3: External Clock Input Operation (HS OSC Configuration)

      34
  • 3.4 PLL Frequency Multiplier

    35
    • FIGURE 3-4: PLL Block Diagram

      35
    • Register 3-1: OSCTUNE: PLL Control Register

      35
  • 3.5 Internal Oscillator Block

    36
  • 3.6 Clock Sources and Oscillator Switching

    36
    • FIGURE 3-5: PIC18F87J10 Family Clock Diagram

      36
    • 3.6.1 Oscillator Control Register

      37
    • 3.6.2 Oscillator Transitions

      37
      • Register 3-2: OSCCON: Oscillator Control Register

        38
  • 3.7 Effects of Power-Managed Modes on the Various Clock Sources

    39
  • 3.8 Power-up Delays

    39
    • TABLE 3-3: OSC1 and OSC2 Pin States in Sleep Mode

      39
• 4.0 Power-Managed Modes

  41
  • 4.1 Selecting Power-Managed Modes

    41
    • 4.1.1 Clock Sources

      41
    • 4.1.2 Entering Power-Managed Modes

      41
      • TABLE 4-1: Power-Managed Modes

        41
    • 4.1.3 Clock Transitions and Status Indicators

      42
    • 4.1.4 Multiple Sleep Commands

      42
  • 4.2 Run Modes

    42
    • 4.2.1 PRI_RUN Mode

      42
    • 4.2.2 SEC_RUN Mode

      42
      • FIGURE 4-1: Transition Timing for Entry to SEC_RUN Mode

        43
      • FIGURE 4-2: Transition Timing From SEC_RUN Mode to PRI_RUN Mode (HSPLL)

        43
    • 4.2.3 RC_RUN Mode

      44
      • FIGURE 4-3: Transition Timing to RC_RUN Mode

        44
      • FIGURE 4-4: Transition Timing From RC_RUN Mode to PRI_RUN Mode

        44
  • 4.3 Sleep Mode

    45
  • 4.4 Idle Modes

    45
    • FIGURE 4-5: Transition Timing for Entry to Sleep Mode

      45
    • FIGURE 4-6: Transition Timing for Wake From Sleep (HSPLL)

      45
    • 4.4.1 PRI_IDLE Mode

      46
    • 4.4.2 SEC_IDLE Mode

      46
      • FIGURE 4-7: Transition Timing for Entry to Idle Mode

        46
      • FIGURE 4-8: Transition Timing for Wake From Idle to Run Mode

        46
    • 4.4.3 RC_IDLE Mode

      47
  • 4.5 Exiting Idle and Sleep Modes

    47
    • 4.5.1 Exit By Interrupt

      47
    • 4.5.2 Exit By WDT Time-out

      47
    • 4.5.3 Exit By Reset

      47
    • 4.5.4 Exit Without an Oscillator Start-up Delay

      47
• 5.0 Reset

  49
  • 5.1 RCON Register

    49
    • FIGURE 5-1: Simplified Block Diagram of On-Chip Reset Circuit

      49
    • Register 5-1: RCON: Reset Control Register

      50
  • 5.2 Master Clear (MCLR)

    51
  • 5.3 Power-on Reset (POR)

    51
  • 5.4 Brown-out Reset (BOR)

    51
    • FIGURE 5-2: External Power-on Reset Circuit (for Slow Vdd Power-up)

      51
    • 5.4.1 Detecting BOR

      51
  • 5.5 Power-up Timer (PWRT)

    52
    • 5.5.1 Time-out Sequence

      52
      • FIGURE 5-3: Time-out Sequence on Power-up (MCLR Tied to Vdd, Vdd Rise < Tpwrt)

        52
      • FIGURE 5-4: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 1

        52
      • FIGURE 5-5: Time-out Sequence on Power-up (MCLR Not Tied to Vdd): Case 2

        53
      • FIGURE 5-6: Slow Rise Time (MCLR Tied to Vdd, Vdd Rise > Tpwrt)

        53
  • 5.6 Reset State of Registers

    54
    • TABLE 5-1: Status Bits, Their Significance and the Initialization Condition for RCON Register

      54
    • TABLE 5-2: Initialization Conditions for All Registers

      55
• 6.0 Memory Organization

  61
  • 6.1 Program Memory Organization

    61
    • FIGURE 6-1: Memory Maps for PIC18F87J10 Family Devices

      61
    • 6.1.1 Hard Memory Vectors

      62
      • FIGURE 6-2: Hard Vector and Configuration Word Locations for PIC18F87J10 Family Devices

        62
    • 6.1.2 Flash Configuration Words

      62
      • TABLE 6-1: Flash Configuration Word for PIC18F87J10 Family Devices

        62
    • 6.1.3 PIC18F8XJ10/8XJ15 Program Memory Modes

      63
      • Register 6-1: CONFIG3L: Configuration Register 3 lOw

        63
    • 6.1.4 Extended Microcontroller Mode and Address Shifting

      64
      • FIGURE 6-3: Memory Maps for PIC18F87J10 Family Program Memory Modes

        64
      • TABLE 6-2: Memory Access for PIC18F8XJ10/8XJ15 Program Memory Modes

        64
    • 6.1.5 Program Counter

      65
    • 6.1.6 Return Address Stack

      65
      • FIGURE 6-4: Return Address Stack and Associated Registers

        65
      • Register 6-2: STKPTR: Stack Pointer Register

        66
    • 6.1.7 Fast Register Stack

      67
      • EXAMPLE 6-1: Fast Register Stack Code Example

        67
    • 6.1.8 Look-up Tables in Program Memory

      67
      • EXAMPLE 6-2: Computed GOTO Using an Offset Value

        67
  • 6.2 PIC18 Instruction Cycle

    68
    • 6.2.1 Clocking Scheme

      68
    • 6.2.2 Instruction Flow/Pipelining

      68
      • FIGURE 6-5: Clock/ Instruction Cycle

        68
      • EXAMPLE 6-3: Instruction Pipeline Flow

        68
    • 6.2.3 Instructions in Program Memory

      69
      • FIGURE 6-6: Instructions in Program Memory

        69
    • 6.2.4 Two-Word Instructions

      69
      • EXAMPLE 6-4: Two-Word Instructions

        69
  • 6.3 Data Memory Organization

    70
    • 6.3.1 Bank Select Register

      70
      • FIGURE 6-7: Data Memory Map for PIC18FX5J10/X5J15/X6J10 Devices

        71
      • FIGURE 6-8: Data Memory Map for PIC18FX6J15/X7J10 Devices

        72
      • FIGURE 6-9: Use of the Bank Select Register (Direct Addressing)

        73
    • 6.3.2 Access Bank

      73
    • 6.3.3 General Purpose Register File

      73
    • 6.3.4 Special Function Registers

      74
      • TABLE 6-3: Special Function Register Map for PIC18F87J10 Family Devices

        74
      • TABLE 6-4: Register File Summary (PIC18F87J10 Family)

        75
    • 6.3.5 STATUS Register

      79
      • Register 6-3: Status Register

        79
  • 6.4 Data Addressing Modes

    80
    • 6.4.1 Inherent and Literal Addressing

      80
    • 6.4.2 Direct Addressing

      80
    • 6.4.3 Indirect Addressing

      80
      • EXAMPLE 6-5: How to Clear RAM (Bank 1) Using Indirect Addressing

        80
      • FIGURE 6-10: Indirect Addressing

        81
  • 6.5 Program Memory and the Extended Instruction Set

    83
  • 6.6 Data Memory and the Extended Instruction Set

    83
    • 6.6.1 Indexed Addressing with Literal Offset

      83
    • 6.6.2 Instructions Affected By Indexed Literal Offset Mode

      83
      • FIGURE 6-11: Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended Instruction Set Enabled)

        84
    • 6.6.3 Mapping the Access Bank in Indexed Literal Offset Mode

      85
    • 6.6.4 BSR in Indexed Literal Offset Mode

      85
      • FIGURE 6-12: Remapping the Access Bank with Indexed Literal Offset Addressing

        85
• 7.0 Flash Program Memory

  87
  • 7.1 Table Reads and Table Writes

    87
    • FIGURE 7-1: Table Read Operation

      87
    • FIGURE 7-2: Table Write Operation

      88
  • 7.2 Control Registers

    88
    • 7.2.1 EECON1 and EECON2 Registers

      88
      • Register 7-1: EECON1: EEPROM Control Register 1

        89
    • 7.2.2 Table Latch Register (TABLAT)

      90
    • 7.2.3 Table Pointer Register (TBLPTR)

      90
    • 7.2.4 Table Pointer Boundaries

      90
      • TABLE 7-1: Table Pointer Operations with TBLRD and TBLWT Instructions

        90
      • FIGURE 7-3: Table Pointer Boundaries Based on Operation

        90
  • 7.3 Reading the Flash Program Memory

    91
    • FIGURE 7-4: Reads from Flash Program Memory

      91
    • EXAMPLE 7-1: Reading a Flash Program Memory Word

      91
  • 7.4 Erasing Flash Program Memory

    92
    • 7.4.1 Flash Program Memory Erase Sequence

      92
      • EXAMPLE 7-2: Erasing Flash Program Memory

        92
  • 7.5 Writing to Flash Program Memory

    93
    • FIGURE 7-5: Table Writes to Flash Program Memory

      93
    • 7.5.1 Flash Program Memory Write Sequence

      93
      • EXAMPLE 7-3: Writing to Flash Program Memory

        94
    • 7.5.2 Write Verify

      95
    • 7.5.3 Unexpected Termination of Write Operation

      95
  • 7.6 Flash Program Operation During Code Protection

    95
    • TABLE 7-2: Registers Associated with Program Flash Memory

      95
• 8.0 External Memory Bus

  97
  • TABLE 8-1: PIC18F8XJ10/8XJ15 External Bus – I/O Port Functions

    97
  • 8.1 External Memory Bus Control

    98
    • Register 8-1: MEMCON: External Memory Bus Control Register

      98
  • 8.2 Address and Data Width

    99
    • 8.2.1 Address Shifting on the External Bus

      99
    • 8.2.2 21-bit Addressing

      99
      • TABLE 8-2: Address and Data Lines for Different Address and Data Widths

        99
  • 8.3 Wait States

    100
  • 8.4 Port Pin Weak Pull-ups

    100
  • 8.5 Program Memory Modes and the External Memory Bus

    100
  • 8.6 16-Bit Data Width Modes

    100
    • 8.6.1 16-Bit Byte Write Mode

      101
      • FIGURE 8-1: 16-Bit Byte Write Mode Example

        101
    • 8.6.2 16-Bit Word Write Mode

      102
      • FIGURE 8-2: 16-Bit Word Write Mode Example

        102
    • 8.6.3 16-Bit Byte Select Mode

      103
      • FIGURE 8-3: 16-Bit Byte Select Mode Example

        103
    • 8.6.4 16-Bit Mode Timing

      104
      • FIGURE 8-4: External Memory Bus Timing for TBLRD (Extended Microcontroller Mode)

        104
      • FIGURE 8-5: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)

        104
  • 8.7 8-Bit Mode

    105
    • FIGURE 8-6: 8-Bit Multiplexed Mode Example

      105
    • 8.7.1 8-Bit Mode Timing

      106
      • FIGURE 8-7: External Memory Bus Timing For TBLRD (Extended Microcontroller Mode)

        106
      • FIGURE 8-8: External Memory Bus Timing for Sleep (Extended Microcontroller Mode)

        106
  • 8.8 Operation in Power-Managed Modes

    107
• 9.0 8 X 8 Hardware Multiplier

  109
  • 9.1 Introduction

    109
  • 9.2 Operation

    109
    • EXAMPLE 9-1: 8 x 8 Unsigned Multiply Routine

      109
    • EXAMPLE 9-2: 8 x 8 Signed Multiply Routine

      109
    • TABLE 9-1: Performance Comparison for Various Multiply Operations

      109
    • EQUATION 9-1: 16 x 16 Unsigned Multiplication Algorithm

      110
    • EXAMPLE 9-3: 16 x 16 Unsigned Multiply Routine

      110
    • EQUATION 9-2: 16 x 16 Signed Multiplication Algorithm

      110
    • EXAMPLE 9-4: 16 x 16 Signed Multiply Routine

      110
• 10.0 Interrupts

  111
  • FIGURE 10-1: PIC18F87J10 family Interrupt Logic

    112
  • 10.1 INTCON Registers

    113
    • Register 10-1: INTCON: Interrupt Control Register

      113
    • Register 10-2: INTCON2: Interrupt Control Register 2

      114
    • Register 10-3: INTCON3: Interrupt Control Register 3

      115
  • 10.2 PIR Registers

    116
    • Register 10-4: PIR1: Peripheral Interrupt Request (Flag) Register 1

      116
    • Register 10-5: PIR2: Peripheral Interrupt Request (Flag) Register 2

      117
    • Register 10-6: PIR3: Peripheral Interrupt Request (Flag) Register 3

      118
  • 10.3 PIE Registers

    119
    • Register 10-7: PIE1: Peripheral Interrupt Enable Register 1

      119
    • Register 10-8: PIE2: Peripheral Interrupt Enable Register 2

      120
    • Register 10-9: PIE3: Peripheral Interrupt Enable Register 3

      121
  • 10.4 IPR Registers

    122
    • Register 10-10: IPR1: Peripheral Interrupt Priority Register 1

      122
    • Register 10-11: IPR2: Peripheral Interrupt Priority Register 2

      123
    • Register 10-12: IPR3: Peripheral Interrupt Priority Register 3

      124
  • 10.5 RCON Register

    125
    • Register 10-13: RCON: Reset Control Register

      125
  • 10.6 INTx Pin Interrupts

    126
  • 10.7 TMR0 Interrupt

    126
  • 10.8 PORTB Interrupt-on-Change

    126
  • 10.9 Context Saving During Interrupts

    126
    • EXAMPLE 10-1: Saving STATUS, WREG and BSR Registers in RAM

      126
• 11.0 I/O Ports

  127
  • FIGURE 11-1: Generic I/O Port Operation

    127
  • 11.1 I/O Port Pin Capabilities

    127
    • 11.1.1 Pin Output Drive

      127
      • TABLE 11-1: Output Drive Levels

        127
    • 11.1.2 Input Pins and Voltage Considerations

      128
      • TABLE 11-2: Input Voltage Levels

        128
  • 11.2 PORTA, TRISA and LATA Registers

    128
    • EXAMPLE 11-1: Initializing PORTA

      128
    • TABLE 11-3: PORTA Functions

      129
    • TABLE 11-4: Summary of Registers Associated with PORTA

      129
  • 11.3 PORTB, TRISB and LATB Registers

    130
    • EXAMPLE 11-2: Initializing PORTB

      130
    • TABLE 11-5: PORTB Functions

      131
    • TABLE 11-6: Summary of Registers Associated with PORTB

      132
  • 11.4 PORTC, TRISC and LATC Registers

    133
    • EXAMPLE 11-3: Initializing PORTC

      133
    • TABLE 11-7: PORTC Functions

      134
    • TABLE 11-8: Summary of Registers Associated with PORTC

      135
  • 11.5 PORTD, TRISD and LATD Registers

    136
    • EXAMPLE 11-4: Initializing PORTD

      136
    • TABLE 11-9: PORTD Functions

      137
    • TABLE 11-10: Summary of Registers Associated with PORTD

      138
  • 11.6 PORTE, TRISE and LATE Registers

    139
    • EXAMPLE 11-5: Initializing PORTE

      139
    • TABLE 11-11: PORTE Functions

      140
    • TABLE 11-12: Summary of Registers Associated with PORTE

      141
  • 11.7 PORTF, LATF and TRISF Registers

    142
    • EXAMPLE 11-6: Initializing PORTF

      142
    • TABLE 11-13: PORTF Functions

      143
    • TABLE 11-14: Summary of Registers Associated with PORTF

      143
  • 11.8 PORTG, TRISG and LATG Registers

    144
    • EXAMPLE 11-7: Initializing PORTG

      144
    • TABLE 11-15: PORTG Functions

      145
    • TABLE 11-16: Summary of Registers Associated with PORTG

      145
  • 11.9 PORTH, LATH and TRISH Registers

    146
    • EXAMPLE 11-8: Initializing PORTH

      146
    • TABLE 11-17: PORTH Functions

      147
    • TABLE 11-18: Summary of Registers Associated with PORTH

      147
  • 11.10 PORTJ, TRISJ and LATJ Registers

    148
    • EXAMPLE 11-9: Initializing PORTJ

      148
    • TABLE 11-19: PORTJ Functions

      149
    • TABLE 11-20: Summary of Registers Associated with PORTJ

      149
  • 11.11 Parallel Slave Port

    150
    • FIGURE 11-2: PORTD and PORTE Block Diagram (Parallel Slave Port)

      150
    • Register 11-1: PSPCON: Parallel Slave Port Control Register

      151
    • FIGURE 11-3: Parallel Slave Port Write Waveforms

      151
    • FIGURE 11-4: Parallel Slave Port Read Waveforms

      152
    • TABLE 11-21: Registers Associated with Parallel Slave Port

      152
• 12.0 Timer0 Module

  153
  • Register 12-1: T0CON: Timer0 Control Register

    153
  • 12.1 Timer0 Operation

    154
  • 12.2 Timer0 Reads and Writes in 16-Bit Mode

    154
    • FIGURE 12-1: Timer0 Block Diagram (8-Bit Mode)

      154
    • FIGURE 12-2: Timer0 Block Diagram (16-bit Mode)

      154
  • 12.3 Prescaler

    155
    • 12.3.1 Switching Prescaler Assignment

      155
  • 12.4 Timer0 Interrupt

    155
    • TABLE 12-1: Registers Associated with Timer0

      155
• 13.0 Timer1 Module

  157
  • Register 13-1: T1CON: Timer1 Control Register

    157
  • 13.1 Timer1 Operation

    158
    • FIGURE 13-1: Timer1 Block Diagram

      158
    • FIGURE 13-2: Timer1 Block Diagram (16-bit Read/Write Mode)

      158
  • 13.2 Timer1 16-Bit Read/Write Mode

    159
  • 13.3 Timer1 Oscillator

    159
    • FIGURE 13-3: External Components for the Timer1 LP Oscillator

      159
    • TABLE 13-1: Capacitor Selection for the Timer Oscillator(2,3,4)

      159
    • 13.3.1 Using Timer1 as a Clock Source

      159
    • 13.3.2 Low-Power Timer1 Option

      159
    • 13.3.3 Timer1 Oscillator Layout Considerations

      160
      • FIGURE 13-4: Oscillator Circuit with Grounded Guard Ring

        160
  • 13.4 Timer1 Interrupt

    160
  • 13.5 Resetting Timer1 Using the ECCP Special Event Trigger

    160
  • 13.6 Using Timer1 as a Real-Time Clock

    160
    • EXAMPLE 13-1: Implementing a Real-Time Clock Using a Timer1 Interrupt Service

      161
    • TABLE 13-2: Registers Associated with Timer1 as a Timer/Counter

      161
• 14.0 Timer2 Module

  163
  • 14.1 Timer2 Operation

    163
    • Register 14-1: T2CON: Timer2 Control Register

      163
  • 14.2 Timer2 Interrupt

    164
  • 14.3 Timer2 Output

    164
    • FIGURE 14-1: Timer2 Block Diagram

      164
    • TABLE 14-1: Registers Associated with Timer2 as a Timer/Counter

      164
• 15.0 Timer3 Module

  165
  • Register 15-1: T3CON: Timer3 Control Register

    165
  • 15.1 Timer3 Operation

    166
    • FIGURE 15-1: Timer3 Block Diagram

      166
    • FIGURE 15-2: Timer3 Block Diagram (16-bit Read/Write Mode)

      166
  • 15.2 Timer3 16-Bit Read/Write Mode

    167
  • 15.3 Using the Timer1 Oscillator as the Timer3 Clock Source

    167
  • 15.4 Timer3 Interrupt

    167
  • 15.5 Resetting Timer3 Using the ECCP Special Event Trigger

    167
    • TABLE 15-1: Registers Associated with Timer3 as a Timer/Counter

      167
• 16.0 Timer4 Module

  169
  • 16.1 Timer4 Operation

    169
    • Register 16-1: T4CON: Timer4 Control Register

      169
  • 16.2 Timer4 Interrupt

    170
  • 16.3 Output of TMR4

    170
    • FIGURE 16-1: Timer4 Block Diagram

      170
    • TABLE 16-1: Registers Associated with Timer4 as a Timer/Counter

      170
• 17.0 Capture/Compare/PWM (CCP) Modules

  171
  • Register 17-1: CCPxCON: CCPx Control Register (CCP4 and CCP5)

    171
  • 17.1 CCP Module Configuration

    172
    • 17.1.1 CCP Modules and Timer Resources

      172
      • TABLE 17-1: CCP Mode – Timer Resource

        172
    • 17.1.2 ECCP2 Pin Assignment

      172
      • FIGURE 17-1: CCP/ECCP and Timer Interconnect Configurations

        172
  • 17.2 Capture Mode

    173
    • 17.2.1 CCP Pin Configuration

      173
    • 17.2.2 Timer1/Timer3 Mode Selection

      173
    • 17.2.3 Software Interrupt

      173
    • 17.2.4 CCP Prescaler

      173
      • EXAMPLE 17-1: Changing Between Capture Prescalers (CCP5 Shown)

        173
      • FIGURE 17-2: Capture Mode Operation Block Diagram

        173
  • 17.3 Compare Mode

    174
    • 17.3.1 CCP Pin Configuration

      174
    • 17.3.2 Timer1/Timer3 Mode Selection

      174
    • 17.3.3 Software Interrupt Mode

      174
      • FIGURE 17-3: Compare Mode Operation Block Diagram

        174
      • TABLE 17-2: Registers Associated with Capture, Compare, Timer1 and Timer3

        175
  • 17.4 PWM Mode

    176
    • FIGURE 17-4: Simplified PWM Block Diagram

      176
    • FIGURE 17-5: PWM Output

      176
    • 17.4.1 PWM Period

      176
      • EQUATION 17-1:

        176
    • 17.4.2 PWM Duty Cycle

      176
      • EQUATION 17-2:

        176
      • EQUATION 17-3:

        177
    • 17.4.3 Setup for PWM Operation

      177
      • TABLE 17-3: Example PWM Frequencies and Resolutions at 40 MHz

        177
      • TABLE 17-4: Registers Associated with PWM, Timer2 and Timer4

        178
• 18.0 Enhanced Capture/ Compare/PWM (ECCP) Module

  179
  • Register 18-1: CCPxCON: Enhanced CCPx Control Register (ECCP1/ECCP2/ECCP3)

    179
  • 18.1 ECCP Outputs and Configuration

    180
    • 18.1.1 ECCP1/ECCP3 Outputs and Program Memory Mode

      180
    • 18.1.2 ECCP2 Outputs and Program Memory Modes

      180
    • 18.1.3 Use of CCP4 and CCP5 with ECCP1 and ECCP3

      180
    • 18.1.4 ECCP Modules and Timer Resources

      180
      • TABLE 18-1: Pin Configurations for ECCP1

        181
      • TABLE 18-2: Pin Configurations for ECCP2

        181
      • TABLE 18-3: Pin Configurations for ECCP3

        182
  • 18.2 Capture and Compare Modes

    182
    • 18.2.1 Special Event Trigger

      182
  • 18.3 Standard PWM Mode

    182
  • 18.4 Enhanced PWM Mode

    183
    • 18.4.1 PWM Period

      183
      • EQUATION 18-1:

        183
      • FIGURE 18-1: Simplified Block Diagram of the Enhanced PWM Module

        183
    • 18.4.2 PWM Duty Cycle

      184
      • EQUATION 18-2:

        184
      • EQUATION 18-3:

        184
    • 18.4.3 PWM Output Configurations

      184
      • TABLE 18-4: Example PWM Frequencies and Resolutions at 40 MHz

        184
      • FIGURE 18-2: PWM Output Relationships (Active-High State)

        185
      • FIGURE 18-3: PWM Output Relationships (Active-Low State)

        185
    • 18.4.4 Half-Bridge Mode

      186
      • FIGURE 18-4: Half-Bridge PWM Output

        186
      • FIGURE 18-5: Examples of Half-Bridge Output Mode Applications

        186
    • 18.4.5 Full-Bridge Mode

      187
      • FIGURE 18-6: Full-Bridge PWM Output

        187
      • FIGURE 18-7: Example of Full-Bridge Application

        188
      • FIGURE 18-8: PWM Direction Change

        189
      • FIGURE 18-9: PWM Direction Change at Near 100% Duty Cycle

        189
    • 18.4.6 Programmable Dead-Band Delay

      190
    • 18.4.7 Enhanced PWM Auto-Shutdown

      190
      • Register 18-2: ECCPxDEL: PWM Dead-Band Delay Register

        190
      • Register 18-3: ECCPxAS: Enhanced CCPx Auto-Shutdown Control Register

        191
    • 18.4.8 Start-up Considerations

      191
      • FIGURE 18-10: PWM Auto-Shutdown (P1RSEN = 1, Auto-Restart Enabled)

        192
      • FIGURE 18-11: PWM Auto-Shutdown (P1RSEN = 0, Auto-Restart Disabled)

        192
    • 18.4.9 Setup for PWM Operation

      193
    • 18.4.10 Effects of a Reset

      193
      • TABLE 18-5: Registers Associated with ECCP Modules and Timer1 to Timer4

        194
• 19.0 Master Synchronous Serial Port (MSSP) Module

  195
  • 19.1 Master SSP (MSSP) Module Overview

    195
  • 19.2 Control Registers

    195
  • 19.3 SPI Mode

    195
    • FIGURE 19-1: MSSP Block Diagram (SPI Mode)

      195
    • 19.3.1 Registers

      196
      • Register 19-1: SSPxSTAT: MSSPx Status Register (SPI Mode)

        196
      • Register 19-2: SSPxCON1: MSSPx Control Register 1 (SPI Mode)

        197
    • 19.3.2 Operation

      198
      • EXAMPLE 19-1: Loading the SSP1BUF (SSP1SR) Register

        198
    • 19.3.3 Enabling SPI I/O

      199
    • 19.3.4 Typical Connection

      199
      • FIGURE 19-2: SPI Master/Slave Connection

        199
    • 19.3.5 Master Mode

      200
      • FIGURE 19-3: SPI Mode Waveform (Master Mode)

        200
    • 19.3.6 Slave Mode

      201
    • 19.3.7 Slave Select Synchronization

      201
      • FIGURE 19-4: Slave Synchronization Waveform

        201
      • FIGURE 19-5: SPI Mode Waveform (Slave Mode with CKE = 0)

        202
      • FIGURE 19-6: SPI Mode Waveform (Slave Mode with CKE = 1)

        202
    • 19.3.8 Operation in Power-Managed Modes

      203
    • 19.3.9 Effects of a Reset

      203
    • 19.3.10 Bus Mode Compatibility

      203
      • TABLE 19-1: SPI Bus Modes

        203
    • 19.3.11 SPI Clock Speed and Module Interactions

      203
      • TABLE 19-2: Registers Associated with SPI Operation

        204
  • 19.4 I2C Mode

    205
    • FIGURE 19-7: MSSP Block Diagram (I2C™ Mode)

      205
    • 19.4.1 Registers

      205
      • Register 19-3: SSPxSTAT: MSSPx Status Register (I2C™ Mode)

        206
      • Register 19-4: SSPxCON1: MSSPx Control Register 1 (I2C™ Mode)

        207
      • Register 19-5: SSPxCON2: MSSPx Control Register 2 (I2C™ Mode)

        208
      • Register 19-6: SSPxADD: MSSP1 and MSSP2 Address Register(1)

        210
    • 19.4.2 Operation

      211
    • 19.4.3 Slave Mode

      211
      • EXAMPLE 19-2: Address Masking

        212
      • FIGURE 19-8: I2C™ Slave Mode Timing with SEN = 0 (Reception, 7-bit Addressing)

        214
      • FIGURE 19-9: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01011 (Reception, 7-bit Addressing)

        215
      • FIGURE 19-10: I2C™ Slave Mode Timing (Transmission, 7-bit Addressing)

        216
      • FIGURE 19-11: I2C™ Slave Mode Timing with SEN = 0 and ADMSK<5:1> = 01001 (Reception, 10-bit Addressing)

        217
      • FIGURE 19-12: I2C™ Slave Mode Timing with SEN = 0 (Reception, 10-bit Addressing)

        218
      • FIGURE 19-13: I2C™ Slave Mode Timing (Transmission, 10-bit Addressing)

        219
    • 19.4.4 Clock Stretching

      220
      • FIGURE 19-14: Clock Synchronization Timing

        221
      • FIGURE 19-15: I2C™ Slave Mode Timing with SEN = 1 (Reception, 7-bit Addressing)

        222
      • FIGURE 19-16: I2C™ Slave Mode Timing with SEN = 1 (Reception, 10-bit Addressing)

        223
    • 19.4.5 General Call Address Support

      224
      • FIGURE 19-17: Slave Mode General Call Address Sequence (7 or 10-bit Addressing Mode)

        224
    • 19.4.6 Master Mode

      225
      • FIGURE 19-18: MSSP Block Diagram (I2C™ Master Mode)

        225
    • 19.4.7 Baud Rate

      227
      • FIGURE 19-19: Baud Rate Generator Block Diagram

        227
      • TABLE 19-3: I2C™ Clock Rate w/BRG

        227
      • FIGURE 19-20: Baud Rate Generator Timing with Clock Arbitration

        228
    • 19.4.8 I2C Master Mode Start Condition Timing

      229
      • FIGURE 19-21: First Start Bit Timing

        229
    • 19.4.9 I2C Master Mode Repeated Start Condition Timing

      230
      • FIGURE 19-22: Repeated Start Condition Waveform

        230
    • 19.4.10 I2C Master Mode Transmission

      231
    • 19.4.11 I2C Master Mode Reception

      231
      • FIGURE 19-23: I2C™ Master Mode Waveform (Transmission, 7 or 10-bit Addressing)

        232
      • FIGURE 19-24: I2C™ Master Mode Waveform (Reception, 7-bit Addressing)

        233
    • 19.4.12 Acknowledge Sequence Timing

      234
    • 19.4.13 Stop Condition Timing

      234
      • FIGURE 19-25: Acknowledge Sequence Waveform

        234
      • FIGURE 19-26: Stop Condition Receive or Transmit Mode

        234
    • 19.4.14 Sleep Operation

      235
    • 19.4.15 Effects of a Reset

      235
    • 19.4.16 Multi-master Mode

      235
    • 19.4.17 Multi -master Communication, Bus Collision and Bus Arbitration

      235
      • FIGURE 19-27: Bus Collision Timing for Transmit and Acknowledge

        235
      • FIGURE 19-28: Bus Collision During Start Condition (SDAx Only)

        236
      • FIGURE 19-29: Bus Collision During Start Condition (SCLx = 0)

        237
      • FIGURE 19-30: BRG Reset Due to SDAx Arbitration During Start Condition

        237
      • FIGURE 19-31: Bus Collision During a Repeated Start Condition (Case 1)

        238
      • FIGURE 19-32: Bus Collision During Repeated Start Condition (Case 2)

        238
      • FIGURE 19-33: Bus Collision During a Stop Condition (Case 1)

        239
      • FIGURE 19-34: Bus Collision During a Stop Condition (Case 2)

        239
      • TABLE 19-4: Registers Associated with I2C™ Operation

        240
• 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  241
  • Register 20-1: TXSTAx: Transmit Status And Control Register

    242
  • Register 20-2: RCSTAx: Receive Status And Control Register

    243
  • Register 20-3: BAUDCONx: Baud Rate Control Register

    244
  • 20.1 Baud Rate Generator (BRG)

    245
    • 20.1.1 Operation in Power-Managed Modes

      245
    • 20.1.2 Sampling

      245
      • TABLE 20-1: Baud Rate Formulas

        245
      • EXAMPLE 20-1: Calculating Baud Rate Error

        246
      • TABLE 20-2: Registers Associated with Baud Rate Generator

        246
      • TABLE 20-3: Baud Rates for Asynchronous Modes

        247
    • 20.1.3 Auto-Baud Rate Detect

      249
      • TABLE 20-4: BRG Counter Clock Rates

        249
      • FIGURE 20-1: Automatic Baud Rate Calculation

        250
      • FIGURE 20-2: BRG Overflow Sequence

        250
  • 20.2 EUSART Asynchronous Mode

    251
    • 20.2.1 EUSART Asynchronous Transmitter

      251
      • FIGURE 20-3: EUSART Transmit Block Diagram

        251
      • FIGURE 20-4: Asynchronous Transmission

        252
      • FIGURE 20-5: Asynchronous Transmission (Back to Back)

        252
      • TABLE 20-5: Registers Associated with Asynchronous Transmission

        252
    • 20.2.2 EUSART Asynchronous Receiver

      253
    • 20.2.3 Setting Up 9-bit Mode with Address Detect

      253
      • FIGURE 20-6: EUSART Receive Block Diagram

        253
      • FIGURE 20-7: Asynchronous Reception

        254
      • TABLE 20-6: Registers Associated with Asynchronous Reception

        254
    • 20.2.4 Auto-Wake-up on Sync Break Character

      254
      • FIGURE 20-8: Auto-Wake-up Bit (WUE) Timings During Normal Operation

        255
      • FIGURE 20-9: Auto-Wake-up Bit (WUE) Timings During Sleep

        255
    • 20.2.5 Break Character Sequence

      256
    • 20.2.6 Receiving A Break Character

      256
      • FIGURE 20-10: Send Break Character Sequence

        256
  • 20.3 EUSART Synchronous Master Mode

    257
    • 20.3.1 EUSART Synchronous Master Transmission

      257
      • FIGURE 20-11: Synchronous Transmission

        257
      • FIGURE 20-12: Synchronous Transmission (Through TXEN)

        258
      • TABLE 20-7: Registers Associated with Synchronous Master Transmission

        258
    • 20.3.2 EUSART Synchronous Master Reception

      259
      • FIGURE 20-13: Synchronous Reception (Master Mode, SREN)

        259
      • TABLE 20-8: Registers Associated with Synchronous Master Reception

        259
  • 20.4 EUSART Synchronous Slave Mode

    260
    • 20.4.1 EUSART Synchronous Slave Transmission

      260
      • TABLE 20-9: Registers Associated with Synchronous Slave Transmission

        260
    • 20.4.2 EUSART Synchronous Slave Reception

      261
      • TABLE 20-10: Registers Associated with Synchronous Slave Reception

        261
• 21.0 10-Bit Analog-to-Digital Converter (A/D) Module

  263
  • Register 21-1: ADCON0: A/D Control Register 0

    263
  • Register 21-2: ADCON1: A/D Control Register 1

    264
  • Register 21-3: ADCON2: A/D Control Register 2

    265
  • FIGURE 21-1: A/D Block Diagram

    266
  • FIGURE 21-2: Analog Input Model

    267
  • 21.1 A/D Acquisition Requirements

    268
    • EQUATION 21-1: Acquisition Time

      268
    • EQUATION 21-2: A/D Minimum Charging Time

      268
    • EQUATION 21-3: Calculating the Minimum Required Acquisition Time

      268
  • 21.2 Selecting and Configuring Automatic Acquisition Time

    269
  • 21.3 Selecting the A/D Conversion Clock

    269
    • TABLE 21-1: Tad vs. Device Operating Frequencies

      269
  • 21.4 Configuring Analog Port Pins

    269
  • 21.5 A/D Conversions

    270
  • 21.6 Use of the ECCP2 Trigger

    270
    • FIGURE 21-3: A/D Conversion Tad Cycles (ACQT<2:0> = 000, Tacq = 0)

      270
    • FIGURE 21-4: A/D Conversion Tad Cycles (ACQT<2:0> = 010, Tacq = 4 Tad)

      270
  • 21.7 A/D Converter Calibration

    271
  • 21.8 Operation in Power-Managed Modes

    271
    • TABLE 21-2: Summary of A/D Registers

      271
• 22.0 Comparator Module

  273
  • Register 22-1: CMCON: Comparator Control Register

    273
  • 22.1 Comparator Configuration

    274
    • FIGURE 22-1: Comparator I/O Operating Modes

      274
  • 22.2 Comparator Operation

    275
  • 22.3 Comparator Reference

    275
    • FIGURE 22-2: Single Comparator

      275
    • 22.3.1 External Reference Signal

      275
    • 22.3.2 Internal Reference Signal

      275
  • 22.4 Comparator Response Time

    275
  • 22.5 Comparator Outputs

    275
    • FIGURE 22-3: Comparator Output Block Diagram

      276
  • 22.6 Comparator Interrupts

    276
  • 22.7 Comparator Operation During Sleep

    276
  • 22.8 Effects of a Reset

    276
  • 22.9 Analog Input Connection Considerations

    277
    • FIGURE 22-4: Comparator Analog Input Model

      277
    • TABLE 22-1: Registers Associated with Comparator Module

      277
• 23.0 Comparator Voltage Reference Module

  279
  • 23.1 Configuring the Comparator Voltage Reference

    279
    • Register 23-1: CVRCON: Comparator Voltage Reference Control Register

      279
    • FIGURE 23-1: Comparator Voltage Reference Block Diagram

      280
  • 23.2 Voltage Reference Accuracy/Error

    280
  • 23.3 Operation During Sleep

    280
  • 23.4 Effects of a Reset

    280
  • 23.5 Connection Considerations

    280
    • FIGURE 23-2: Comparator Voltage Reference Output Buffer Example

      281
    • TABLE 23-1: Registers Associated with Comparator Voltage Reference

      281
• 24.0 Special Features of the CPU

  283
  • 24.1 Configuration Bits

    283
    • 24.1.1 Considerations for Configuring the PIC18F87J10 family Devices

      283
      • TABLE 24-1: Mapping of the Flash Configuration Words to the Configuration Registers

        283
      • TABLE 24-2: Configuration Bits and Device IDs

        284
      • Register 24-1: CONFIG1L: Configuration Register 1 Low (Byte Address 300000h)

        285
      • Register 24-2: CONFIG1H: Configuration Register 1 High (Byte Address 300001h)

        285
      • Register 24-3: CONFIG2L: Configuration Register 2 Low (Byte AdDREss 300002h)

        286
      • Register 24-4: CONFIG2H: Configuration Register 2 High (Byte Address 300003h)

        286
      • Register 24-5: CONFIG3L: Configuration Register 3 Low (Byte Address 300004h)

        287
      • Register 24-6: CONFIG3H: Configuration Register 3 High (Byte Address 300005h)

        287
      • Register 24-7: DEVID1: Device ID Register 1 for PIC18F87J10 Family Devices

        288
      • Register 24-8: DEVID2: Device ID Register 2 for PIC18F87J10 Family Devices

        288
  • 24.2 Watchdog Timer (WDT)

    289
    • 24.2.1 Control Register

      289
      • FIGURE 24-1: WDT Block Diagram

        289
      • Register 24-9: WDTCON: Watchdog Timer Control Register

        289
      • TABLE 24-3: Summary of Watchdog Timer Registers

        289
  • 24.3 On-Chip Voltage Regulator

    290
    • 24.3.1 On-Chip Regulator and BOR

      290
    • 24.3.2 Power-up Requirements

      290
      • FIGURE 24-2: Connections for the On-chip Regulator

        290
  • 24.4 Two-Speed Start-up

    291
    • 24.4.1 Special Considerations for Using Two-Speed Start-up

      291
      • FIGURE 24-3: Timing Transition for Two-Speed Start-up (INTRC to HSPLL)

        291
  • 24.5 Fail-Safe Clock Monitor

    292
    • FIGURE 24-4: FSCM Block Diagram

      292
    • 24.5.1 FSCM and the Watchdog Timer

      292
    • 24.5.2 Exiting Fail-Safe Operation

      292
      • FIGURE 24-5: FSCM Timing Diagram

        293
    • 24.5.3 FSCM Interrupts in Power-Managed Modes

      293
    • 24.5.4 POR or Wake-up From Sleep

      293
  • 24.6 Program Verification and Code Protection

    294
    • 24.6.1 Configuration Register Protection

      294
  • 24.7 In-Circuit Serial Programming

    294
  • 24.8 In-Circuit Debugger

    294
    • TABLE 24-4: Debugger Resources

      294
• 25.0 Instruction Set Summary

  295
  • 25.1 Standard Instruction Set

    295
    • TABLE 25-1: Opcode Field Descriptions

      296
    • FIGURE 25-1: General Format for Instructions

      297
    • TABLE 25-2: PIC18F87J10 family Instruction Set

      298
    • 25.1.1 Standard Instruction Set

      301
  • 25.2 Extended Instruction Set

    337
    • 25.2.1 Extended Instruction Syntax

      337
      • TABLE 25-3: Extensions to the PIC18 Instruction Set

        337
    • 25.2.2 Extended Instruction Set

      338
    • 25.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode

      342
    • 25.2.4 Considerations When Enabling the Extended Instruction Set

      342
    • 25.2.5 Special Considerations with Microchip MPLAB® IDE Tools

      344
• 26.0 Development Support

  345
  • 26.1 MPLAB Integrated Development Environment Software

    345
  • 26.2 MPASM Assembler

    346
  • 26.3 MPLAB C18 and MPLAB C30 C Compilers

    346
  • 26.4 MPLINK Object Linker/ MPLIB Object Librarian

    346
  • 26.5 MPLAB ASM30 Assembler, Linker and Librarian

    346
  • 26.6 MPLAB SIM Software Simulator

    346
  • 26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator

    347
  • 26.8 MPLAB REAL ICE In-Circuit Emulator System

    347
  • 26.9 MPLAB ICD 2 In-Circuit Debugger

    347
  • 26.10 MPLAB PM3 Device Programmer

    347
  • 26.11 PICSTART Plus Development Programmer

    348
  • 26.12 PICkit 2 Development Programmer

    348
  • 26.13 Demonstration, Development and Evaluation Boards

    348
• 27.0 Electrical Characteristics

  349
  • Absolute Maximum Ratings(†)

    349
    • FIGURE 27-1: PIC18F87J10 family Voltage-frequency Graph, Regulator Disabled (Industrial)

      350
    • FIGURE 27-2: PIC18F87J10 Family Voltage-Frequency Graph, Regulator Enabled (Industrial)

      351
  • 27.1 DC Characteristics: Supply Voltage, PIC18F87J10 Family (Industrial)

    352
  • 27.2 DC Characteristics: Power-Down and Supply Current PIC18F87J10 Family (Industrial)

    353
  • 27.3 DC Characteristics: PIC18F87J10 Family (Industrial)

    360
    • TABLE 27-1: Memory Programming Requirements

      362
    • TABLE 27-2: Comparator Specifications

      363
    • TABLE 27-3: Voltage Reference Specifications

      363
    • TABLE 27-4: Internal Voltage Regulator Specifications

      363
  • 27.4 AC (Timing) Characteristics

    364
    • 27.4.1 Timing Parameter Symbology

      364
    • 27.4.2 Timing Conditions

      365
      • TABLE 27-5: Temperature and Voltage Specifications – AC

        365
      • FIGURE 27-3: Load Conditions for Device Timing Specifications

        365
    • 27.4.3 Timing Diagrams and Specifications

      366
      • FIGURE 27-4: External Clock Timing (All Modes Except PLL)

        366
      • TABLE 27-6: External Clock Timing Requirements

        366
      • TABLE 27-7: PLL Clock Timing Specifications (Vdd = 2.7V to 3.6V)

        367
      • TABLE 27-8: AC Characteristics: Internal RC Accuracy PIC18F87J10 family (Industrial)

        367
      • FIGURE 27-5: CLKO and I/O Timing

        368
      • TABLE 27-9: CLKO and I/O Timing Requirements

        368
      • FIGURE 27-6: Program Memory Fetch Timing Diagram (8-Bit)

        369
      • TABLE 27-7: Program Memory Fetch Timing Requirements (8-Bit)

        369
      • FIGURE 27-8: Program Memory Read Timing Diagram

        370
      • TABLE 27-10: CLKO and I/O Timing Requirements

        370
      • FIGURE 27-9: Program Memory Write Timing Diagram

        371
      • TABLE 27-11: Program Memory Write Timing Requirements

        371
      • FIGURE 27-10: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

        372
      • TABLE 27-12: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements

        372
      • FIGURE 27-11: Timer0 and Timer1 External Clock Timings

        373
      • TABLE 27-13: Timer0 and Timer1 External Clock Requirements

        373
      • FIGURE 27-12: Capture/Compare/PWM Timings (Including ECCP Modules)

        374
      • TABLE 27-14: Capture/Compare/PWM Requirements (Including ECCP Modules)

        374
      • TABLE 27-15: Parallel Slave Port Requirements

        374
      • FIGURE 27-13: Example SPI Master Mode Timing (CKE = 0)

        375
      • TABLE 27-16: Example SPI Mode Requirements (Master Mode, Cke = 0)

        375
      • FIGURE 27-14: Example SPI Master Mode Timing (CKE = 1)

        376
      • TABLE 27-17: Example SPI Mode Requirements (Master Mode, CKE = 1)

        376
      • FIGURE 27-15: Example SPI Slave Mode Timing (CKE = 0)

        377
      • TABLE 27-18: Example SPI Mode Requirements (Slave Mode Timing, CKE = 0)

        377
      • FIGURE 27-16: Example SPI Slave Mode Timing (CKE = 1)

        378
      • TABLE 27-19: Example SPI Slave Mode Requirements (CKE = 1)

        378
      • FIGURE 27-17: I2C™ Bus Start/Stop Bits Timing

        379
      • TABLE 27-20: I2C™ Bus Start/Stop Bits Requirements (Slave Mode)

        379
      • FIGURE 27-18: I2C™ Bus Data Timing

        379
      • TABLE 27-21: I2C™ Bus Data Requirements (Slave Mode)

        380
      • FIGURE 27-19: Master SSP I2C™ Bus Start/Stop Bits Timing Waveforms

        381
      • TABLE 27-22: Master SSP I2C™ Bus Start/Stop Bits Requirements

        381
      • FIGURE 27-20: Master SSP I2C™ Bus Data Timing

        381
      • TABLE 27-23: Master SSP I2C™ Bus Data Requirements

        382
      • FIGURE 27-21: EUSART Synchronous Transmission (Master/Slave) Timing

        383
      • TABLE 27-24: EUSART Synchronous Transmission Requirements

        383
      • FIGURE 27-22: EUSART Synchronous Receive (Master/Slave) Timing

        383
      • TABLE 27-25: EUSART Synchronous Receive Requirements

        383
      • TABLE 27-26: A/D Converter Characteristics: PIC18F87J10 family (Industrial)

        384
      • FIGURE 27-23: A/D Conversion Timing

        384
      • TABLE 27-27: A/D Conversion Requirements

        385
• 28.0 Packaging Information

  387
  • 28.1 Package Marking Information

    387
  • 28.2 Package Details

    388
• Appendix A: Migration Between High-End Device Families

  393
  • TABLE A-1: Notable Differences Between PIC18F8722 and PIC18F87J10 Families

    393
• Appendix B: Revision History

  395
  • Revision A (December 2004)

    395
  • Revision B (July 2005)

    395
  • Revision C (December 2005)

    395
  • Revision D (June 2006)

    395
  • Revision E (June 2009)

    395
  • Revision F (September 2009)

    395
• Index

  397
• The Microchip Web Site

  407
• Customer Change Notification Service

  407
• Customer Support

  407
• Reader Response

  408
• Product Identification System

  409
• Worldwide Sales and Service

  410