Manuais de utilizador para Microchip Technology MA240017

índice analítico

• Power Management Modes:

  3
• High-Performance CPU:

  3
• Peripheral Features:

  3
• Analog Features:

  3
• Special Microcontroller Features:

  3
• Pin Diagrams

  4
• Pin Diagrams (Continued)

  5
• Pin Diagrams (Continued)

  6
• Table of Contents

  7
• Most Current Data Sheet

  8
• Errata

  8
• Customer Notification System

  8
• 1.0 Device Overview

  9
  • 1.1 Core Features

    9
    • 1.1.1 16-bit architecture

      9
    • 1.1.2 Power-saving Technology

      9
    • 1.1.3 Oscillator Options and Features

      9
    • 1.1.4 Easy Migration

      10
  • 1.2 Other Special Features

    10
  • 1.3 Details on Individual Family Members

    10
    • TABLE 1-1: Device Features for the PIC24F16KA102 family

      11
    • FIGURE 1-1: PIC24F16KA102 family General Block Diagram

      12
    • TABLE 1-2: PIC24F16KA102 family Pinout Descriptions

      13
• 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers

  17
  • 2.1 Basic Connection Requirements

    17
    • FIGURE 2-1: Recommended Minimum connections

      17
  • 2.2 Power Supply Pins

    18
  • 2.3 Master Clear (MCLR) Pin

    18
    • FIGURE 2-2: Example of MCLR Pin Connections

      18
  • 2.4 Voltage Regulator Pin (Vcap)

    19
    • FIGURE 2-3: Frequency vs. ESR Performance for Suggested Vcap

      19
    • TABLE 2-1: Suitable Capacitor Equivalents

      19
    • FIGURE 2-4: DC Bias Voltage vs. Capacitance Characteristics

      20
  • 2.5 ICSP Pins

    20
  • 2.6 External Oscillator Pins

    21
  • 2.7 Unused I/Os

    21
    • FIGURE 2-5: Suggested Placement of the Oscillator Circuit

      21
• 3.0 CPU

  23
  • 3.1 Programmer’s Model

    23
    • FIGURE 3-1: PIC24F CPU Core Block Diagram

      24
    • TABLE 3-1: CPU Core Registers

      24
    • FIGURE 3-2: Programmer’s Model

      25
  • 3.2 CPU Control Registers

    26
    • Register 3-1: SR: ALU STATUS Register

      26
    • Register 3-2: CORCON: CPU Control Register

      27
  • 3.3 Arithmetic Logic Unit (ALU)

    27
    • 3.3.1 Multiplier

      27
    • 3.3.2 Divider

      28
    • 3.3.3 Multi-Bit Shift Support

      28
      • TABLE 3-2: Instructions that Use the Single and Multi-Bit Shift Operation

        28
• 4.0 Memory Organization

  29
  • 4.1 Program Address Space

    29
    • FIGURE 4-1: Program Space Memory Map for PIC24F16KA102 family Devices

      29
    • 4.1.1 Program Memory Organization

      30
    • 4.1.2 Hard Memory Vectors

      30
    • 4.1.3 Data EEPROM

      30
    • 4.1.4 Device Configuration Words

      30
      • TABLE 4-1: Device Configuration Words for PIC24F16KA102 family Devices

        30
      • FIGURE 4-2: Program Memory Organization

        30
  • 4.2 Data Address Space

    31
    • 4.2.1 Data Space Width

      31
      • FIGURE 4-3: Data Space Memory Map for PIC24F16KA102 family Devices

        31
    • 4.2.2 Data Memory Organization and Alignment

      32
    • 4.2.3 Near Data Space

      32
    • 4.2.4 SFR Space

      32
      • TABLE 4-2: Implemented Regions of SFR Data Space

        32
      • TABLE 4-3: CPU Core Registers Map

        33
      • TABLE 4-4: ICN Register Map

        34
      • TABLE 4-5: Interrupt Controller Register Map

        34
      • TABLE 4-6: Timer Register Map

        35
      • TABLE 4-7: Input Capture Register Map

        35
      • TABLE 4-8: Output Compare Register Map

        35
      • TABLE 4-9: I2C™ Register Map

        36
      • TABLE 4-10: UART Register Map

        36
      • TABLE 4-11: SPI Register Map

        36
      • TABLE 4-12: PORTA Register Map

        37
      • TABLE 4-13: PORTB Register Map

        37
      • TABLE 4-14: Pad Configuration Register Map

        37
      • TABLE 4-15: A/D Register Map

        38
      • TABLE 4-16: CTMU Register Map

        38
      • TABLE 4-17: Real-Time Clock and Calendar Register Map

        39
      • TABLE 4-18: Dual Comparator Register Map

        39
      • TABLE 4-19: CRC Register Map

        39
      • TABLE 4-20: Clock Control Register Map

        40
      • TABLE 4-21: Deep Sleep Register Map

        40
      • TABLE 4-22: NVM Register Map

        40
      • TABLE 4-23: PMD Register Map

        40
    • 4.2.5 Software Stack

      41
      • FIGURE 4-4: CALL Stack Frame

        41
  • 4.3 Interfacing Program and Data Memory Spaces

    41
    • 4.3.1 Addressing Program Space

      41
      • TABLE 4-24: Program Space Address Construction

        42
      • FIGURE 4-5: Data Access From Program Space Address Generation

        42
    • 4.3.2 Data Access From Program Memory and Data EEPROM Memory Using Table Instructions

      43
      • FIGURE 4-6: Accessing Program Memory with Table Instructions

        43
    • 4.3.3 Reading Data From Program Memory Using Program Space Visibility

      44
      • FIGURE 4-7: Program Space Visibility Operation

        44
• 5.0 Flash Program Memory

  45
  • 5.1 Table Instructions and Flash Programming

    45
    • FIGURE 5-1: Addressing for Table Registers

      45
  • 5.2 RTSP Operation

    46
  • 5.3 Enhanced In-Circuit Serial Programming

    46
  • 5.4 Control Registers

    46
  • 5.5 Programming Operations

    46
    • Register 5-1: NVMCON: Flash Memory Control Register

      47
    • 5.5.1 Programming Algorithm for Flash Program Memory

      48
      • EXAMPLE 5-1: Erasing a Program Memory Row – Assembly Language Code

        48
      • EXAMPLE 5-2: Erasing a Program Memory Row – ‘C’ Language Code

        48
      • EXAMPLE 5-3: Loading the Write Buffers – Assembly Language Code

        49
      • EXAMPLE 5-4: Loading the Write Buffers – ‘C’ Language Code

        49
      • EXAMPLE 5-5: Initiating a Programming Sequence – Assembly Language Code

        50
      • EXAMPLE 5-6: Initiating a Programming Sequence – ‘C’ Language Code

        50
• 6.0 Data EEPROM Memory

  51
  • 6.1 NVMCON Register

    51
  • 6.2 NVMKEY Register

    51
    • EXAMPLE 6-1: Data EEPROM Unlock Sequence

      51
    • Register 6-1: NVMCON: Nonvolatile Memory Control Register

      52
  • 6.3 NVM Address Register

    53
    • FIGURE 6-1: Data EEPROM Addressing with TBLPAG and NVM Address Registers

      53
  • 6.4 Data EEPROM Operations

    53
    • 6.4.1 Erase Data EEPROM

      54
      • EXAMPLE 6-2: Single-Word Erase

        54
    • 6.4.2 Single-Word Write

      55
      • EXAMPLE 6-3: Data EEPROM Bulk Erase

        55
      • EXAMPLE 6-4: Single-Word Write to Data EEPROM

        55
    • 6.4.3 Reading the Data EEPROM

      56
      • EXAMPLE 6-5: Reading the Data EEPROM Using the TBLRD Command

        56
• 7.0 Resets

  57
  • FIGURE 7-1: Reset System Block Diagram

    57
  • Register 7-1: RCON: Reset Control Register(1)

    58
  • TABLE 7-1: Reset Flag Bit Operation

    59
  • 7.1 Clock Source Selection at Reset

    60
    • TABLE 7-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)

      60
  • 7.2 Device Reset Times

    60
    • TABLE 7-3: Reset Delay Times for Various Device Resets

      60
    • 7.2.1 POR and Long Oscillator Start-up Times

      61
    • 7.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets

      61
  • 7.3 Special Function Register Reset States

    61
  • 7.4 Deep Sleep BOR (DSBOR)

    61
  • 7.5 Brown-out Reset (BOR)

    61
    • 7.5.1 Software Enabled BOR

      61
    • 7.5.2 Detecting BOR

      62
    • 7.5.3 Disabling BOR in Sleep Mode

      62
• 8.0 Interrupt Controller

  63
  • 8.1 Interrupt Vector (IVT) Table

    63
    • 8.1.1 Alternate Interrupt Vector Table (AIVT)

      63
  • 8.2 Reset Sequence

    63
    • FIGURE 8-1: PIC24F Interrupt Vector Table

      64
    • TABLE 8-1: Trap Vector Details

      65
    • TABLE 8-2: Implemented Interrupt Vectors

      65
  • 8.3 Interrupt Control and Status Registers

    66
    • Register 8-1: SR: ALU STATUS Register

      67
    • Register 8-2: CORCON: CPU Control Register

      68
    • Register 8-3: INTCON1: Interrupt Control Register 1

      69
    • Register 8-4: INTCON2: Interrupt Control Register2

      70
    • Register 8-5: IFS0: Interrupt Flag Status Register 0

      71
    • Register 8-6: IFS1: Interrupt Flag Status Register 1

      72
    • Register 8-7: IFS3: Interrupt Flag Status Register 3

      73
    • Register 8-8: IFS4: Interrupt Flag Status Register 4

      74
    • Register 8-9: IEC0: Interrupt Enable Control Register 0

      75
    • Register 8-10: IEC1: Interrupt Enable Control Register 1

      76
    • Register 8-11: IEC3: Interrupt Enable Control Register 3

      77
    • Register 8-12: IEC4: Interrupt Enable Control Register 4

      78
    • Register 8-13: IPC0: Interrupt Priority Control Register 0

      79
    • Register 8-14: IPC1: Interrupt Priority Control Register 1

      80
    • Register 8-15: IPC2: Interrupt Priority Control Register 2

      81
    • Register 8-16: IPC3: Interrupt Priority Control Register 3

      82
    • Register 8-17: IPC4: Interrupt Priority Control Register 4

      83
    • Register 8-18: IPC5: Interrupt Priority Control Register 5

      84
    • Register 8-19: IPC7: Interrupt Priority Control Register 7

      85
    • Register 8-20: IPC15: Interrupt Priority Control Register 15

      86
    • Register 8-21: IPC16: Interrupt Priority Control Register 16

      87
    • Register 8-22: IPC18: Interrupt Priority Control Register 18

      88
    • Register 8-23: IPC19: Interrupt Priority Control Register 19

      88
    • Register 8-24: INTTREG: Interrupt Control and Status Register

      89
  • 8.4 Interrupt Setup Procedures

    90
    • 8.4.1 Initialization

      90
    • 8.4.2 Interrupt Service Routine

      90
    • 8.4.3 Trap Service Routine (TSR)

      90
    • 8.4.4 Interrupt Disable

      90
• 9.0 Oscillator Configuration

  91
  • FIGURE 9-1: PIC24F16KA102 family Clock Diagram

    91
  • 9.1 CPU Clocking Scheme

    92
  • 9.2 Initial Configuration on POR

    92
    • 9.2.1 Clock Switching Mode Configuration Bits

      92
      • TABLE 9-1: Configuration Bit Values for Clock Selection

        92
  • 9.3 Control Registers

    93
    • Register 9-1: OSCCON: Oscillator Control Register

      93
    • Register 9-2: CLKDIV: Clock Divider Register

      95
    • Register 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER

      96
  • 9.4 Clock Switching Operation

    97
    • 9.4.1 Enabling Clock Switching

      97
    • 9.4.2 Oscillator Switching Sequence

      97
      • EXAMPLE 9-1: Basic Code Sequence For Clock Switching

        98
  • 9.5 Reference Clock Output

    98
    • Register 9-4: REFOCON: Reference Oscillator Control Register

      99
• 10.0 Power-Saving Features

  101
  • 10.1 Clock Frequency and Clock Switching

    101
  • 10.2 Instruction-Based Power-Saving Modes

    101
    • 10.2.1 Sleep Mode

      101
      • EXAMPLE 10-1: PWRSAV Instruction Syntax

        101
    • 10.2.2 Idle Mode

      102
    • 10.2.3 Interrupts Coincident with Power Save Instructions

      102
    • 10.2.4 Deep Sleep Mode

      102
      • Register 10-1: DSCON: Deep Sleep Control Register(1)

        105
      • Register 10-2: DSWAKE: Deep Sleep Wake-Up Source Register(1)

        106
  • 10.3 Doze Mode

    107
  • 10.4 Selective Peripheral Module Control

    107
    • Register 10-3: PMD1: Peripheral Module Disable Register 1

      108
    • Register 10-4: PMD2: Peripheral Module Disable Register 2

      109
    • Register 10-5: PMD3: Peripheral Module Disable Register 3

      110
    • Register 10-6: PMD4: Peripheral Module Disable Register 4

      111
• 11.0 I/O Ports

  113
  • 11.1 Parallel I/O (PIO) Ports

    113
    • FIGURE 11-1: Block Diagram of a Typical Shared Port Structure

      113
    • 11.1.1 Open-Drain Configuration

      114
  • 11.2 Configuring Analog Port Pins

    114
    • 11.2.1 I/O Port Write/Read Timing

      114
  • 11.3 Input Change Notification

    114
    • EXAMPLE 11-1: Port Write/Read Example

      114
• 12.0 Timer1

  115
  • FIGURE 12-1: 16-Bit Timer1 Module Block Diagram

    115
  • Register 12-1: T1CON: Timer1 Control Register

    116
• 13.0 Timer2/3

  117
  • FIGURE 13-1: Timer2/3 (32-Bit) Block Diagram

    118
  • FIGURE 13-2: timer2 (16-Bit Synchronous) Block Diagram

    119
  • FIGURE 13-3: Timer3 (16-Bit Synchronous) Block Diagram

    119
  • Register 13-1: T2CON: Timer2 Control Register

    120
  • Register 13-2: T3CON: Timer3 Control Register

    121
• 14.0 Input Capture

  123
  • FIGURE 14-1: Input Capture Block Diagram

    123
  • 14.1 Input Capture Registers

    124
    • Register 14-1: IC1CON: Input Capture 1 Control Register

      124
• 15.0 Output Compare

  125
  • 15.1 Setup for Single Output Pulse Generation

    125
  • 15.2 Setup for Continuous Output Pulse Generation

    125
  • 15.3 Pulse-Width Modulation (PWM) Mode

    126
    • 15.3.1 PWM Period

      126
      • EQUATION 15-1: Calculating the PWM Period(1)

        126
    • 15.3.2 PWM Duty Cycle

      126
      • EQUATION 15-2: Calculation for Maximum PWM Resolution(1)

        126
      • EXAMPLE 15-1: PWM Period and Duty Cycle Calculations(1)

        127
      • TABLE 15-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)(1)

        127
      • TABLE 15-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)(1)

        127
      • FIGURE 15-1: Output Compare Module Block Diagram

        128
  • 15.4 Output Compare Register

    129
    • Register 15-1: OC1CON: Output Compare 1 Control Register

      129
    • Register 15-2: PADCFG1: Pad Configuration Control Register

      130
• 16.0 Serial Peripheral Interface (SPI)

  131
  • FIGURE 16-1: SPI1 Module Block Diagram (Standard Buffer Mode)

    132
  • FIGURE 16-2: SPI1 Module Block Diagram (Enhanced Buffer Mode)

    133
  • Register 16-1: SPI1STAT: SPI1 Status and Control Register

    134
  • Register 16-2: SPI1CON1: SPI1 Control Register 1

    136
  • Register 16-3: SPI1CON2: SPI1 Control Register 2

    137
  • EQUATION 16-1: Relationship Between Device and Spi Clock Speed(1)

    138
  • TABLE 16-1: Sample SCK Frequencies(1,2)

    138
• 17.0 Inter-Integrated Circuit (I2C™)

  139
  • 17.1 Pin Remapping Options

    139
  • 17.2 Communicating as a Master in a Single Master Environment

    139
    • FIGURE 17-1: I2C™ Block Diagram

      140
  • 17.3 Setting Baud Rate When Operating as a Bus Master

    141
    • EQUATION 17-1: Computing Baud Rate Reload Value(1)

      141
  • 17.4 Slave Address Masking

    141
    • TABLE 17-1: I2C™ Clock Rates(1)

      141
    • TABLE 17-2: I2C™ Reserved Addresses(1)

      141
    • Register 17-1: I2C1CON: I2C1 Control Register

      142
    • Register 17-2: I2C1STAT: I2C1 Status Register

      144
    • Register 17-3: I2C1MSK: I2C1 Slave Mode Address Mask Register

      146
    • Register 17-4: PADCFG1: Pad Configuration Control Register

      146
• 18.0 Universal Asynchronous Receiver Transmitter (UART)

  147
  • FIGURE 18-1: UART Simplified Block Diagram

    147
  • 18.1 UART Baud Rate Generator (BRG)

    148
    • EQUATION 18-1: UART Baud Rate with BRGH = 0(1)

      148
    • EQUATION 18-2: UART Baud Rate with BRGH = 1(1)

      148
    • EXAMPLE 18-1: Baud Rate Error Calculation (BRGH = 0)(1)

      148
  • 18.2 Transmitting in 8-Bit Data Mode

    149
  • 18.3 Transmitting in 9-Bit Data Mode

    149
  • 18.4 Break and Sync Transmit Sequence

    149
  • 18.5 Receiving in 8-Bit or 9-Bit Data Mode

    149
  • 18.6 Operation of UxCTS and UxRTS Control Pins

    149
  • 18.7 Infrared Support

    149
    • 18.7.1 External IrDA Support – IrDA Clock Output

      149
    • 18.7.2 Built-in IrDA Encoder and Decoder

      149
      • Register 18-1: UxMODE: UARTx Mode Register

        150
      • Register 18-2: UxSTA: UARTx Status and Control Register

        152
      • Register 18-3: UxTXREG: UARTx Transmit Register

        154
      • Register 18-4: UxRXREG: UARTx Receive Register

        154
• 19.0 Real-Time Clock and Calendar (RTCC)

  155
  • 19.1 RTCC Source Clock

    155
    • FIGURE 19-1: RTCC Block Diagram

      155
  • 19.2 RTCC Module Registers

    156
    • 19.2.1 Register Mapping

      156
      • TABLE 19-1: RTCVAL Register Mapping

        156
      • TABLE 19-2: ALRMVAL Register Mapping

        156
    • 19.2.2 Write Lock

      156
    • 19.2.3 Selecting RTCC Clock Source

      156
      • EXAMPLE 19-1: Setting the RTCWREN Bit

        156
    • 19.2.4 RTCC Control Registers

      157
      • Register 19-1: RCFGCAL: RTCC Calibration and Configuration Register(1)

        157
      • Register 19-2: PADCFG1: Pad Configuration Control Register

        158
      • Register 19-3: ALCFGRPT: Alarm Configuration Register

        159
    • 19.2.5 RTCVAL Register Mappings

      160
      • Register 19-4: YEAR: Year Value Register(1)

        160
      • Register 19-5: MTHDY: Month and Day Value Register(1)

        160
      • Register 19-6: WKDYHR: Weekday and Hours Value Register(1)

        161
      • Register 19-7: MINSEC: Minutes and Seconds Value Register

        161
    • 19.2.6 ALRMVAL Register Mappings

      162
      • Register 19-8: ALMTHDY: Alarm Month and Day Value Register(1)

        162
      • Register 19-9: ALWDHR: Alarm Weekday and Hours Value Register(1)

        162
      • Register 19-10: ALMINSEC: Alarm Minutes and Seconds Value Register

        163
  • 19.3 Calibration

    164
    • EQUATION 19-1:

      164
  • 19.4 Alarm

    164
    • 19.4.1 Configuring The Alarm

      164
    • 19.4.2 Alarm Interrupt

      164
      • FIGURE 19-2: Alarm Mask Settings

        165
• 20.0 Programmable Cyclic Redundancy Check (CRC) Generator

  167
  • EQUATION 20-1: CRC

    167
  • TABLE 20-1: Example CRC Setup

    167
  • FIGURE 20-1: CRC Shifter Details

    167
  • FIGURE 20-2: CRC Generator Reconfigured for x16 + x12 + x5 + 1

    168
  • 20.1 User Interface

    168
    • 20.1.1 Data Interface

      168
    • 20.1.2 Interrupt Operation

      168
  • 20.2 Operation in Power Save Modes

    168
    • 20.2.1 Sleep Mode

      168
    • 20.2.2 Idle Mode

      168
  • 20.3 Registers

    169
    • Register 20-1: CRCCON: CRC Control Register

      169
    • Register 20-2: CRCXOR: CRC XOR Polynomial Register

      170
• 21.0 High/Low-Voltage Detect (HLVD)

  171
  • FIGURE 21-1: High/Low-Voltage Detect (HLVD) Module Block Diagram

    171
  • Register 21-1: HLVDCON: High/Low-Voltage Detect Control Register

    172
• 22.0 10-Bit High-Speed A/D Converter

  173
  • FIGURE 22-1: 10-Bit High-Speed A/D Converter Block Diagram

    174
  • Register 22-1: AD1CON1: A/D Control Register 1

    175
  • Register 22-2: AD1CON2: A/D Control Register 2

    176
  • Register 22-3: AD1CON3: A/D Control Register 3

    177
  • Register 22-4: AD1CHS: A/D Input Select Register

    178
  • Register 22-5: AD1PCFG: A/D Port Configuration Register

    179
  • Register 22-6: AD1CSSL: A/D Input Scan Select Register (Low)

    180
  • EQUATION 22-1: A/D Conversion Clock Period(1)

    181
  • FIGURE 22-2: 10-bit A/D Converter Analog Input Model

    181
  • FIGURE 22-3: A/D Transfer Function

    182
• 23.0 Comparator Module

  183
  • FIGURE 23-1: Comparator Module Block Diagram

    183
  • FIGURE 23-2: Individual Comparator Configurations

    184
  • Register 23-1: CMxCON: Comparator x Control Registers

    185
  • Register 23-2: CMSTAT: Comparator Module Status Register

    186
• 24.0 Comparator Voltage Reference

  187
  • 24.1 Configuring the Comparator Voltage Reference

    187
    • FIGURE 24-1: Comparator Voltage Reference Block Diagram

      187
    • Register 24-1: CVRCON: Comparator Voltage Reference Control Register

      188
• 25.0 Charge Time Measurement Unit (CTMU)

  189
  • 25.1 Measuring Capacitance

    189
    • FIGURE 25-1: Typical Connections and Internal Configuration for Capacitance Measurement

      189
  • 25.2 Measuring Time

    190
  • 25.3 Pulse Generation and Delay

    190
    • FIGURE 25-2: Typical Connections and Internal Configuration for Time Measurement

      190
    • FIGURE 25-3: Typical Connections and Internal Configuration for Pulse Delay Generation

      190
    • Register 25-1: CTMUCON: CTMU Control Register

      191
    • Register 25-2: CTMUICON: CTMU current Control Register

      192
• 26.0 Special Features

  193
  • 26.1 Configuration Bits

    193
    • TABLE 26-1: CONFIGURATION Registers LOCATIONS

      193
    • Register 26-1: FBS: Boot Segment Configuration Register

      193
    • Register 26-2: FGS: General Segment Configuration Register

      194
    • Register 26-3: FoscSEL: Oscillator Selection Configuration Register

      194
    • Register 26-4: Fosc: Oscillator Configuration Register

      195
    • Register 26-5: FWDT: Watchdog Timer Configuration Register

      196
    • Register 26-6: FPOR: Reset Configuration Register

      197
    • Register 26-7: FICD: In-Circuit Debugger Configuration Register

      198
    • Register 26-8: FDS: Deep Sleep Configuration Register

      199
    • Register 26-9: DEVID: Device ID Register

      200
    • Register 26-10: DEVREV: Device Revision Register

      200
  • 26.2 Watchdog Timer (WDT)

    201
    • 26.2.1 Windowed Operation

      201
    • 26.2.2 Control Register

      201
      • FIGURE 26-1: WDT Block Diagram

        201
  • 26.3 Deep Sleep Watchdog Timer (DSWDT)

    202
  • 26.4 Program Verification and Code Protection

    202
  • 26.5 In-Circuit Serial Programming

    202
  • 26.6 In-Circuit Debugger

    202
  • 27.0 Development Support

    203
• 28.0 Instruction Set Summary

  207
  • TABLE 28-1: Symbols Used in Opcode Descriptions

    208
  • TABLE 28-2: Instruction Set Overview

    209
• 29.0 Electrical Characteristics

  215
  • Absolute Maximum Ratings(†)

    215
  • 29.1 DC Characteristics

    216
    • FIGURE 29-1: PIC24F16KA102 family Voltage-Frequency Graph (Industrial)

      216
    • FIGURE 29-2: PIC24F16KA102 family Voltage-frequency Graph (Industrial, Extended)

      216
    • TABLE 29-1: Thermal Operating Conditions

      217
    • TABLE 29-2: Thermal Packaging Characteristics

      217
    • TABLE 29-3: DC Characteristics: Temperature and Voltage Specifications

      218
    • TABLE 29-4: High/Low–Voltage Detect Characteristics

      218
    • FIGURE 29-3: BROWN-OUT RESET CHARACTERISTICS

      219
    • TABLE 29-5: BOR Trip Points

      219
    • TABLE 29-6: DC Characteristics: Operating Current (Idd)

      220
    • TABLE 29-7: DC Characteristics: Idle Current (Iidle)

      222
    • TABLE 29-8: DC Characteristics: Power-Down Current (Ipd)

      224
    • TABLE 29-9: DC Characteristics: I/O Pin Input Specifications

      227
    • TABLE 29-10: DC Characteristics: I/O Pin Output Specifications

      228
    • TABLE 29-11: DC Characteristics: Program Memory

      229
    • TABLE 29-12: DC Characteristics: Data EEPROM Memory

      229
    • TABLE 29-13: Comparator DC Specifications

      230
    • TABLE 29-14: Comparator Voltage Reference DC Specifications

      230
    • TABLE 29-15: Internal Voltage References

      230
    • TABLE 29-16: CTMU Current Source Specifications

      230
  • 29.2 AC Characteristics and Timing Parameters

    231
    • TABLE 29-17: Temperature and Voltage Specifications – AC

      231
    • FIGURE 29-4: Load Conditions for Device Timing Specifications

      231
    • TABLE 29-18: Capacitive Loading Requirements on Output Pins

      231
    • FIGURE 29-5: External Clock Timing

      232
    • TABLE 29-19: External Clock Timing Requirements

      232
    • TABLE 29-20: PLL Clock Timing Specifications (Vdd = 1.8V to 3.6V)

      233
    • TABLE 29-21: AC Characteristics: Internal RC Accuracy

      233
    • TABLE 29-22: AC Specifications

      234
    • TABLE 29-23: A/D Conversion TiminG Requirements(1)

      234
    • TABLE 29-24: A/D Module Specifications

      235
    • FIGURE 29-6: CLKO and I/O Timing Characteristics

      236
    • TABLE 29-25: CLKO and I/O Timing Requirements

      236
    • TABLE 29-26: Comparator Timings

      237
    • TABLE 29-27: Comparator Voltage Reference Settling Time Specifications

      237
    • FIGURE 29-7: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      238
    • TABLE 29-28: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements

      239
    • FIGURE 29-8: Baud Rate Generator Output Timing

      239
    • FIGURE 29-9: I2C™ Bus Start/Stop Bits Timing Characteristics (Master Mode)

      240
    • TABLE 29-29: I2C™ Bus Start/Stop Bit Timing Requirements (Master Mode)

      240
    • FIGURE 29-10: I2C™ Bus Data Timing Characteristics (Master Mode)

      240
    • TABLE 29-30: I2C™ Bus Data Timing Requirements (Master Mode)

      241
    • FIGURE 29-11: I2C™ Bus Start/Stop Bits Timing Characteristics (Slave Mode)

      242
    • FIGURE 29-12: I2C™ Bus Data Timing Characteristics (Slave Mode)

      242
    • TABLE 29-31: I2C™ Bus Start/Stop Bit Timing Requirements (Slave Mode)

      242
    • TABLE 29-32: I2C™ Bus Data Timing Requirements (Slave Mode)

      243
    • FIGURE 29-13: Start Bit Edge Detection

      243
    • FIGURE 29-14: Input Capture Timings

      244
    • TABLE 29-33: Input Capture

      244
    • TABLE 29-34: Output Capture

      244
    • FIGURE 29-15: Output Compare Timings

      244
    • FIGURE 29-16: PWM Module Timing Requirements

      245
    • TABLE 29-35: PWM Timing Requirements

      245
    • FIGURE 29-17: SPIx Module Master Mode Timing Characteristics (CKE = 0)

      246
    • TABLE 29-36: SPIx Master Mode Timing Requirements (CKE = 0)

      246
    • FIGURE 29-18: SPIx Module Master Mode Timing Characteristics (CKE = 1)

      247
    • TABLE 29-37: SPIx Module Master Mode Timing Requirements (CKE = 1)

      247
    • FIGURE 29-19: SPIx Module Slave Mode Timing Characteristics (CKE = 0)

      248
    • TABLE 29-38: SPIx Module Slave Mode Timing Requirements (CKE = 0)

      248
    • FIGURE 29-20: SPIx Module Slave Mode Timing Characteristics (CKE = 1)

      249
    • TABLE 29-39: SPIx Module Slave Mode Timing Requirements (CKE = 1)

      249
• 30.0 Packaging Information

  251
  • 30.1 Package Marking Information

    251
  • 30.2 Package Details

    253
• Appendix A: Revision History

  269
  • Revision A (November 2008)

    269
  • Revision B (March 2009)

    269
  • Revision C (October 2011)

    269
• INDEX

  271
• The Microchip Web Site

  275
• Customer Change Notification Service

  275
• Customer Support

  275
• Reader Response

  276
• Product Identification System

  277
• Worldwide Sales and Service

  278