Ficha De Dadosíndice analíticoOperating Conditions1Core: 16-Bit dsPIC33F CPU1Clock Management1Power Management1High-Speed PWM1Advanced Analog Features1Advanced Analog Features (Continued)1Timers/Output Compare/Input Capture1Communication Interfaces1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 Product Families2TABLE 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families2Pin Diagrams3Pin Diagrams (Continued)4Pin Diagrams (Continued)5Pin Diagrams (Continued)6Pin Diagrams (Continued)7Pin Diagrams (Continued)8Pin Diagrams (Continued)9Pin Diagrams (Continued)10Pin Diagrams (Continued)11Pin Diagrams (Continued)12Table of Contents13Most Current Data Sheet14Errata14Customer Notification System14Referenced Sources151.0 Device Overview17FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Block Diagram18TABLE 1-1: Pinout I/O Descriptions192.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers212.1 Basic Connection Requirements212.2 Decoupling Capacitors21FIGURE 2-1: Recommended Minimum Connection222.2.1 Tank Capacitors222.3 Capacitor on Internal Voltage Regulator (Vcap)222.4 Master Clear (MCLR) Pin22FIGURE 2-2: Example of MCLR Pin Connections222.5 ICSP™ Pins232.6 External Oscillator Pins23FIGURE 2-3: Suggested Placement of the Oscillator Circuit232.7 Oscillator Value Conditions on Device Start-up232.8 Configuration of Analog and Digital Pins During ICSP Operations242.9 Unused I/Os242.10 Typical Application Connection Examples24FIGURE 2-4: Digital PFC25FIGURE 2-5: boost Converter Implementation25FIGURE 2-6: Single-Phase Synchronous Buck converter26FIGURE 2-7: Multi-Phase Synchronous Buck converter26FIGURE 2-8: Off-Line UPS27FIGURE 2-9: interleaved PFC28FIGURE 2-10: Phase-Shifted Full-Bridge Converter29FIGURE 2-11: AC-to-DC Power Supply with PFC and Three Outputs (12V, 5V and 3.3V)303.0 CPU313.1 Data Addressing Overview313.2 DSP Engine Overview313.3 Special MCU Features32FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU Core Block Diagram32FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Programmer’s Model333.4 CPU Control Registers34Register 3-1: SR: CPU STATUS Register34Register 3-2: CORCON: CORE Control Register363.5 Arithmetic Logic Unit (ALU)383.5.1 Multiplier383.5.2 Divider383.6 DSP Engine38TABLE 3-1: DSP Instructions Summary38FIGURE 3-3: DSP Engine Block Diagram393.6.1 Multiplier403.6.2 Data Accumulators and Adder/Subtracter403.6.3 Accumulator ‘Write Back’413.6.4 Barrel Shifter424.0 Memory Organization434.1 Program Address Space43FIGURE 4-1: Program Memory Maps for dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Devices434.1.1 Program Memory Organization444.1.2 Interrupt and Trap Vectors44FIGURE 4-2: Program Memory Organization444.2 Data Address Space454.2.1 Data Space Width454.2.2 Data Memory Organization and Alignment454.2.3 SFR Space454.2.4 Near Data Space45FIGURE 4-3: Data Memory Map for dsPIC33FJ06GS101/102 Devices with 256 bytes of RAM46FIGURE 4-4: Data Memory Map for dsPIC33FJ06GS202 Device with 1-Kbyte RAM47FIGURE 4-5: Data Memory Map for dsPIC33FJ16GS402/404/502/504 Devices with 2-KBYTE RAM484.2.5 X and Y Data Spaces49TABLE 4-1: CPU Core Register Map50TABLE 4-2: Change Notification Register Map for dsPIC33FJ06GS10151TABLE 4-3: Change Notification Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS50251TABLE 4-4: Change Notification Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS50451TABLE 4-5: Interrupt Controller Register Map for dsPIC33FJ06GS101 Devices Only52TABLE 4-6: Interrupt Controller Register Map for dsPIC33FJ06GS102 Devices Only53TABLE 4-7: Interrupt Controller Register Map for dsPIC33FJ06G202 Devices Only54TABLE 4-8: Interrupt Controller Register Map for dsPIC33FJ16GS402/404 Devices Only55TABLE 4-9: Interrupt Controller Register Map for dsPIC33FJ16GS502 Devices Only56TABLE 4-10: Interrupt Controller Register Map for dsPIC33FJ16GS504 Devices Only57TABLE 4-11: Timer Register Map for dsPIC33FJ06GS101 and dsPIC33FJ06GSx0258TABLE 4-12: Timer Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ16GSX0458TABLE 4-13: Input Capture Register Map for dsPIC33FJ06GS20258TABLE 4-14: Input Capture Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ16GSX0459TABLE 4-15: Output Compare Register Map for dsPIC33FJ06GS101 and dsPIC33FJ06GSX0259TABLE 4-16: Output Compare Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ06GSX0459TABLE 4-17: High-Speed PWM Register Map59TABLE 4-18: High-Speed PWM Generator 1 Register Map60TABLE 4-19: High-Speed PWM Generator 2 Register Map for dsPIC33FJ06GS102/202 and dsPIC33FJ16GSX02/X04 Devices Only60TABLE 4-20: High-Speed PWM Generator 3 Register Map for dsPIC33FJ16GSX02/X04 Devices Only61TABLE 4-21: High-Speed PWM Generator 4 Register Map for dsPIC33FJ06GS101 and dsPIC33FJ16GS50X Devices Only61TABLE 4-22: I2C1 Register Map62TABLE 4-23: UART1 Register Map62TABLE 4-24: SPI1 Register Map62TABLE 4-25: High-Speed 10-Bit ADC Register Map for dsPIC33FJ06GS101 devices Only63TABLE 4-26: High-Speed 10-Bit ADC Register Map for dsPIC33FJ06GS102 Devices Only63TABLE 4-27: High-Speed 10-bit ADC Register Map for dsPIC33FJ06GS202 Devices Only64TABLE 4-28: High-Speed 10-bit ADC Register Map for dsPIC33FJ16GS402/404 Devices Only64TABLE 4-29: High-Speed 10-bit ADC Register Map for dsPIC33FJ16GS502 Devices Only65TABLE 4-30: High-Speed 10-Bit ADC Register Map for dsPIC33FJ16GS504 Devices Only66TABLE 4-31: Analog Comparator Control Register Map for dsPIC33FJ06GS202 Devices Only67TABLE 4-32: Analog Comparator Control Register Map dsPIC33FJ16GS502/504 Devices Only67TABLE 4-33: Peripheral Pin Select Input Register Map68TABLE 4-34: Peripheral Pin Select Output Register Map for dsPIC33FJ06GS10168TABLE 4-35: Peripheral Pin Select Output Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 and dsPIC33FJ16GS50269TABLE 4-36: Peripheral Pin Select Output Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS50469TABLE 4-37: PORTA Register Map70TABLE 4-38: PORTB Register Map for dsPIC33FJ06GS10170TABLE 4-39: PORTB Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404, dsPIC33FJ16GS502 and dsPIC33FJ16GS50470TABLE 4-40: PORTC Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS50470TABLE 4-41: System Control Register Map71TABLE 4-42: NVM Register Map71TABLE 4-43: PMD Register Map for dsPIC33FJ06GS101 Devices Only71TABLE 4-44: PMD Register Map for dsPIC33FJ06GS102 Devices Only71TABLE 4-45: PMD REGISTER MAP for dsPIC33FJ06GS202 Devices Only72TABLE 4-46: PMD Register Map for dsPIC33FJ16GS402 and dsPIC33FJ16GS404 Devices Only72TABLE 4-47: PMD Register Map for dsPIC33FJ16GS502 and dsPIC33FJ16GS504 Devices Only724.2.6 Software Stack73FIGURE 4-6: CALL Stack Frame734.3 Instruction Addressing Modes734.3.1 File Register Instructions734.3.2 MCU Instructions73TABLE 4-48: Fundamental Addressing Modes Supported744.3.3 Move and Accumulator Instructions744.3.4 MAC Instructions744.3.5 Other Instructions744.4 Modulo Addressing754.4.1 Start and End Address754.4.2 W Address Register Selection75FIGURE 4-7: Modulo Addressing Operation Example754.4.3 Modulo Addressing Applicability764.5 Bit-Reversed Addressing764.5.1 Bit-Reversed Addressing Implementation76FIGURE 4-8: Bit-Reversed Address Example77TABLE 4-49: Bit-Reversed Address Sequence (16-Entry)774.6 Interfacing Program and Data Memory Spaces784.6.1 Addressing Program Space78TABLE 4-50: Program Space Address Construction78FIGURE 4-9: Data Access from Program Space Address Generation794.6.2 Data Access from Program Memory Using Table Instructions80FIGURE 4-10: Accessing Program Memory with Table Instructions804.6.3 Reading Data from Program Memory Using Program Space Visibility81FIGURE 4-11: Program Space Visibility Operation815.0 Flash Program Memory835.1 Table Instructions and Flash Programming83FIGURE 5-1: Addressing for Table Registers835.2 RTSP Operation845.3 Programming Operations84EQUATION 5-1: Programming Time84EQUATION 5-2: Minimum Row Write Time84EQUATION 5-3: Maximum Row Write Time845.4 Control Registers84Register 5-1: NVMCON: Flash Memory Control Register85Register 5-2: NVMKEY: Nonvolatile Memory Key Register865.4.1 Programming Algorithm for Flash Program Memory87EXAMPLE 5-1: Erasing a Program Memory Page87EXAMPLE 5-2: Loading the Write Buffers88EXAMPLE 5-3: Initiating a Programming Sequence886.0 Resets89FIGURE 6-1: Reset System Block Diagram89Register 6-1: RCON: Reset Control Register(1)906.1 System Reset92TABLE 6-1: Oscillator Delay92FIGURE 6-2: System Reset Timing93TABLE 6-2: Oscillator Delay936.2 Power-on Reset (POR)946.2.1 Brown-out Reset (BOR) and Power-up Timer (PWRT)94FIGURE 6-3: Brown-out Situations946.3 External Reset (EXTR)956.3.0.1 External Supervisory Circuit956.3.0.2 Internal Supervisory Circuit956.4 Software RESET Instruction (SWR)956.5 Watchdog Timer Time-out Reset (WDTO)956.6 Trap Conflict Reset956.7 Configuration Mismatch Reset956.8 Illegal Condition Device Reset956.8.1 Illegal Opcode Reset956.8.2 Uninitialized W Register Reset966.8.3 Security Reset966.9 Using the RCON Status Bits96TABLE 6-3: Reset Flag Bit Operation967.0 Interrupt Controller977.1 Interrupt Vector Table977.1.1 Alternate Interrupt Vector Table977.2 Reset Sequence97FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Interrupt Vector Table98TABLE 7-1: Interrupt Vectors997.3 Interrupt Control and Status Registers1007.3.1 INTCON1 and INTCON21007.3.2 IFSx1007.3.3 IECx1007.3.4 IPCx1007.3.5 INTTREG1007.3.6 Status/Control Registers100Register 7-1: SR: CPU STATUS Register(1)101Register 7-2: CORCON: CORE Control Register(1)101Register 7-3: INTCON1: Interrupt Control Register 1102Register 7-4: INTCON2: Interrupt Control Register 2104Register 7-5: IFS0: Interrupt Flag Status Register 0105Register 7-6: IFS1: Interrupt Flag Status Register 1107Register 7-7: IFS3: Interrupt Flag Status Register 3108Register 7-8: IFS4: Interrupt Flag Status Register 4108Register 7-9: IFS5: Interrupt Flag Status Register 5109Register 7-10: IFS6: Interrupt Flag Status Register 6110Register 7-11: IFS7: Interrupt Flag Status Register 7111Register 7-12: IEC0: Interrupt Enable Control Register 0112Register 7-13: IEC1: Interrupt Enable Control Register 1114Register 7-14: IEC3: Interrupt Enable Control Register 3115Register 7-15: IEC4: Interrupt Enable Control Register 4115Register 7-16: IEC5: Interrupt Enable Control Register 5116Register 7-17: IEC6: Interrupt Enable Control Register 6117Register 7-18: IEC7: Interrupt Enable Control Register 7118Register 7-19: IPC0: Interrupt Priority Control Register 0119Register 7-20: IPC1: Interrupt Priority Control Register 1120Register 7-21: IPC2: Interrupt Priority Control Register 2121Register 7-22: IPC3: Interrupt Priority Control Register 3122Register 7-23: IPC4: Interrupt Priority Control Register 4123Register 7-24: IPC5: Interrupt Priority Control Register 5124Register 7-25: IPC7: Interrupt Priority Control Register 7124Register 7-26: IPC14: Interrupt Priority Control Register 14125Register 7-27: IPC16: Interrupt Priority Control Register 16125Register 7-28: IPC23: Interrupt Priority Control Register 23126Register 7-29: IPC24: Interrupt Priority Control Register 24127Register 7-30: IPC25: Interrupt Priority Control Register 25128Register 7-31: IPC26: Interrupt Priority Control Register 26129Register 7-32: IPC27: Interrupt Priority Control Register 27130Register 7-33: IPC28: Interrupt Priority Control Register 28131Register 7-34: IPC29: Interrupt Priority Control Register 29132Register 7-35: INTTREG: Interrupt Control and Status Register1337.4 Interrupt Setup Procedures1347.4.1 Initialization1347.4.2 Interrupt Service Routine1347.4.3 Trap Service Routine1347.4.4 Interrupt Disable1348.0 Oscillator Configuration135FIGURE 8-1: Oscillator System Diagram1358.1 CPU Clocking System1368.1.1 System Clock Sources1368.1.2 System Clock Selection136EQUATION 8-1: Device Operating Frequency136TABLE 8-1: Configuration Bit Values for Clock Selection1368.1.3 PLL Configuration137EQUATION 8-2: Fosc Calculation137EQUATION 8-3: XT with PLL Mode Example137FIGURE 8-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL Block Diagram1378.2 Auxiliary Clock Generation1388.3 Reference Clock Generation1388.4 Oscillator Control Registers139Register 8-1: OSCCON: Oscillator Control Register(1,2)139Register 8-2: CLKDIV: Clock Divisor Register(1)141Register 8-3: PLLFBD: PLL Feedback Divisor Register(1)142Register 8-4: OSCTUN: FRC Oscillator Tuning Register(1)143Register 8-5: ACLKCON: Auxiliary Clock Divisor Control Register(1)144Register 8-6: REFOCON: Reference Oscillator Control Register1458.5 Clock Switching Operation1468.5.1 Enabling Clock Switching1468.5.2 Oscillator Switching Sequence1468.6 Fail-Safe Clock Monitor (FSCM)1469.0 Power-Saving Features1479.1 Clock Frequency and Clock Switching1479.2 Instruction-Based Power-Saving Modes1479.2.1 Sleep Mode147EXAMPLE 9-1: PWRSAV Instruction Syntax1479.2.2 Idle Mode1489.2.3 Interrupts Coincident with Power Save Instructions1489.3 Doze Mode1489.4 Peripheral Module Disable148Register 9-1: PMD1: Peripheral Module Disable Control Register 1149Register 9-2: PMD2: Peripheral Module Disable Control Register 2150Register 9-3: PMD3: Peripheral Module Disable Control Register 3151Register 9-4: PMD4: Peripheral Module Disable Control Register 4151Register 9-5: PMD6: Peripheral Module Disable Control Register 6152Register 9-6: PMD7: Peripheral Module Disable Control Register 715310.0 I/O Ports15510.1 Parallel I/O (PIO) Ports155FIGURE 10-1: Block Diagram of a Typical Shared Port Structure15510.2 Open-Drain Configuration15610.3 Configuring Analog Port Pins15610.4 I/O Port Write/Read Timing15610.5 Input Change Notification156EQUATION 10-1: Port Write/Read Example15610.6 Peripheral Pin Select15710.6.1 Available Pins15710.6.2 Controlling Peripheral Pin Select157FIGURE 10-2: Remappable MUX Input for U1RX157TABLE 10-1: Selectable Input Sources (Maps Input To Function)158FIGURE 10-3: Multiplexing of Remappable Output for RPn159TABLE 10-2: Output Selection for Remappable Pin (RPn)15910.6.3 Controlling Configuration Changes16010.7 Peripheral Pin Select Registers161Register 10-1: RPINR0: Peripheral Pin Select Input Register 0161Register 10-2: RPINR1: Peripheral Pin Select Input Register 1162Register 10-3: RPINR3: Peripheral Pin Select Input Register 3163Register 10-4: RPINR7: Peripheral Pin Select Input Register 7164Register 10-5: RPINR11: Peripheral Pin Select Input Register 11165Register 10-6: RPINR18: Peripheral Pin Select Input Register 18166Register 10-7: RPINR20: Peripheral Pin Select Input Register 20167Register 10-8: RPINR21: Peripheral Pin Select Input Register 21168Register 10-9: RPINR29: Peripheral Pin Select Input Register 29169Register 10-10: RPINR30: Peripheral Pin Select Input Register 30170Register 10-11: RPINR31: Peripheral Pin Select Input Register 31171Register 10-12: RPINR32: Peripheral Pin Select Input Register 32172Register 10-13: RPINR33: Peripheral Pin Select Input Register 33173Register 10-14: RPINR34: Peripheral Pin Select Input Register 34174Register 10-15: RPOR0: Peripheral Pin Select Output Register 0174Register 10-16: RPOR1: Peripheral Pin Select Output Register 1175Register 10-17: RPOR2: Peripheral Pin Select Output Register 2175Register 10-18: RPOR3: Peripheral Pin Select Output Register 3176Register 10-19: RPOR4: Peripheral Pin Select Output Register 4(1)176Register 10-20: RPOR5: Peripheral Pin Select Output Register 5(1)177Register 10-21: RPOR6: Peripheral Pin Select Output Register 6(1)177Register 10-22: RPOR7: Peripheral Pin Select Output Register 7(1)178Register 10-23: RPOR8: Peripheral Pin Select Output Register 8(1)178Register 10-24: RPOR9: Peripheral Pin Select Output Register 9(1)179Register 10-25: RPOR10: Peripheral Pin Select Output Register 10(1)179Register 10-26: RPOR11: Peripheral Pin Select Output Register 11(1)180Register 10-27: RPOR12: Peripheral Pin Select Output Register 12(1)180Register 10-28: RPOR13: Peripheral Pin Select Output Register 13(1)181Register 10-29: RPOR14: Peripheral Pin Select Output Register 14(1)181Register 10-30: RPOR16: Peripheral Pin Select Output Register 16182Register 10-31: RPOR17: Peripheral Pin Select Output Register 1718211.0 Timer1183TABLE 11-1: Timer Mode Settings183FIGURE 11-1: 16-bit Timer1 Module Block Diagram183Register 11-1: T1CON: Timer1 Control Register18412.0 Timer2/3 Features185FIGURE 12-1: Type B Timer Block Diagram (x = 2)185FIGURE 12-2: Type C Timer Block Diagram (X = 3)185TABLE 12-1: Timer Mode Settings18612.1 16-Bit Operation18612.2 32-Bit Operation186TABLE 12-2: 32-bit Timer186FIGURE 12-3: 32-Bit Timer Block Diagram187Register 12-1: TxCON: Timerx Control Register (x = 2)188Register 12-2: TyCON: Timery Control Register (y = 3)18913.0 Input Capture191FIGURE 13-1: Input Capture x Block Diagram19113.1 Input Capture Register192Register 13-1: ICxCON: Input Capture x Control Register (x = 1, 2)19214.0 Output Compare193FIGURE 14-1: Output Compare x Module Block Diagram19314.1 Output Compare Modes194TABLE 14-1: Output Compare Modes194FIGURE 14-2: Output Compare Operation194Register 14-1: OCxCON: Output Compare x Control Register (x = 1, 2)19515.0 High-Speed PWM19715.1 Features Overview19715.2 Feature Description198FIGURE 15-1: Simplified Conceptual Block Diagram of High-Speed PWM199FIGURE 15-2: Partitioned Output Pair, Complementary PWM Mode20015.3 Control Registers200Register 15-1: PTCON: PWM Time Base Control Register201Register 15-2: PTCON2: PWM Clock Divider Select Register203Register 15-3: PTPER: PWM Master Time Base Register(1)203Register 15-4: SEVTCMP: PWM Special Event Compare Register204Register 15-5: MDC: PWM Master Duty Cycle Register(1,2)204Register 15-6: PWMCONx: PWMx Control Register205Register 15-7: PDCx: PWMx Generator Duty Cycle Register(1,2)207Register 15-8: SDCx: PWMx Secondary Duty Cycle Register(1,2)207Register 15-9: PHASEx: PWMx Primary Phase-Shift Register(1,2)208Register 15-10: SPHASEx: PWMx Secondary Phase-Shift Register(1,2)209Register 15-11: DTRx: PWMx Dead-Time Register210Register 15-12: ALTDTRx: PWMx Alternate Dead-Time Register210Register 15-13: TRGCONx: PWMx Trigger Control Register211Register 15-14: IOCONx: PWMx I/O Control Register212Register 15-15: FCLCONx: PWMx Fault Current-Limit Control Register214Register 15-16: TRIGx: PWMx Primary Trigger Compare Value Register216Register 15-17: STRIGx: PWMx Secondary Trigger Compare Value Register216Register 15-18: LEBCONx: Leading-Edge Blanking Control Register(1)217Register 15-19: PWMCAPx: Primary PWMx Time Base Capture Register21816.0 Serial Peripheral Interface (SPI)219FIGURE 16-1: SPIx Module Block Diagram219Register 16-1: SPIxSTAT: SPIx Status and Control Register220Register 16-2: SPIxCON1: SPIx Control Register 1221Register 16-3: SPIxCON2: SPIx Control Register 222317.0 Inter-Integrated Circuit (I2C™)22517.1 Operating Modes225FIGURE 17-1: I2Cx Block Diagram (x = 1)22617.2 I2C Registers227Register 17-1: I2CxCON: I2Cx Control Register228Register 17-2: I2CxSTAT: I2Cx Status Register230Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register23218.0 Universal Asynchronous Receiver Transmitter (UART)233Register 18-1: UxMODE: UARTx Mode Register234Register 18-2: UxSTA: UARTx Status and Control Register23619.0 High-Speed 10-bit Analog-to-Digital Converter (ADC)23919.1 Features Overview23919.2 Module Description23919.3 Module Functionality239FIGURE 19-1: ADC Block Diagram for dsPIC33FJ06GS101 Devices with One SAR240FIGURE 19-2: ADC Block Diagram for dsPIC33FJ06GS102 Devices with One SAR241FIGURE 19-3: ADC Block Diagram for dsPIC33FJ06GS202 Devices with One SAR242FIGURE 19-4: ADC Block Diagram for dsPIC33FJ16GS402/404 Devices with One SAR243FIGURE 19-5: ADC Block Diagram for dsPIC33FJ16GS502 Devices with Two SARS244FIGURE 19-6: ADC Block Diagram for dsPIC33FJ16GS504 devices with two SARs24519.4 ADC Control Registers246Register 19-1: ADCON: Analog-to-Digital Control Register247Register 19-2: ADSTAT: Analog-to-Digital Status Register249Register 19-3: ADBASE: Analog-to-Digital Base Register(1,2)250Register 19-4: ADPCFG: Analog-to-Digital Port Configuration Register250Register 19-5: ADCPC0: Analog-to-Digital Convert Pair Control Register 0251Register 19-6: ADCPC1: Analog-to-Digital Convert Pair Control Register 1254Register 19-7: ADCPC2: Analog-to-Digital Convert Pair Control Register 2(1)257Register 19-8: ADCPC3: Analog-to-Digital Convert Pair Control Register 3(1)26020.0 High-Speed Analog Comparator26320.1 Features Overview26320.2 Module Description263FIGURE 20-1: High-Speed Analog Comparator Module Block Diagram26320.3 Module Applications26420.4 DAC26420.5 Interaction with I/O Buffers26420.6 Digital Logic26420.7 Comparator Input Range26420.8 DAC Output Range26420.9 Comparator Registers264Register 20-1: CMPCONx: Comparator Control x Register265Register 20-2: CMPDACx: Comparator DAC x Control Register26621.0 Special Features26721.1 Configuration Bits267TABLE 21-1: Device Configuration Register Map267TABLE 21-2: dsPIC33F Configuration Bits Description26821.2 On-Chip Voltage Regulator270FIGURE 21-1: Connections for the On-Chip Voltage Regulator(1,2,3)27021.3 BOR: Brown-out Reset27021.4 Watchdog Timer (WDT)27121.4.1 Prescaler/Postscaler27121.4.2 Sleep and Idle Modes27121.4.3 Enabling WDT271FIGURE 21-2: WDT Block diagram27121.5 JTAG Interface27221.6 In-Circuit Serial Programming27221.7 In-Circuit Debugger27221.8 Code Protection and CodeGuard™ Security273TABLE 21-3: Code Flash Security Segment Sizes for 6-Kbyte Devices273TABLE 21-4: Code Flash Security Segment Sizes for 16-Kbyte Devices27322.0 Instruction Set Summary275TABLE 22-1: Symbols Used in Opcode Descriptions276TABLE 22-2: Instruction Set Overview27823.0 Development Support28323.1 MPLAB X Integrated Development Environment Software28323.2 MPLAB XC Compilers28423.3 MPASM Assembler28423.4 MPLINK Object Linker/ MPLIB Object Librarian28423.5 MPLAB Assembler, Linker and Librarian for Various Device Families28423.6 MPLAB X SIM Software Simulator28523.7 MPLAB REAL ICE In-Circuit Emulator System28523.8 MPLAB ICD 3 In-Circuit Debugger System28523.9 PICkit 3 In-Circuit Debugger/ Programmer28523.10 MPLAB PM3 Device Programmer28523.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits28623.12 Third-Party Development Tools28624.0 Electrical Characteristics287Absolute Maximum Ratings(1)28724.1 DC Characteristics288TABLE 24-1: Operating MIPS vs. Voltage288TABLE 24-2: Thermal Operating Conditions288TABLE 24-3: Thermal Packaging Characteristics288TABLE 24-4: DC Temperature and Voltage specifications289TABLE 24-5: DC Characteristics: Operating Current (Idd)290TABLE 24-6: DC Characteristics: Idle Current (Iidle)292TABLE 24-7: DC Characteristics: Power-Down Current (Ipd)293TABLE 24-8: DC Characteristics: Doze Current (Idoze)294TABLE 24-9: DC Characteristics: I/O Pin Input Specifications295TABLE 24-10: DC Characteristics: I/O Pin Output Specifications297TABLE 24-11: Electrical Characteristics: BOR298TABLE 24-12: DC Characteristics: Program Memory299TABLE 24-13: Internal Voltage Regulator Specifications29924.2 AC Characteristics and Timing Parameters300TABLE 24-14: Temperature and Voltage Specifications – AC300FIGURE 24-1: Load Conditions for Device Timing Specifications300TABLE 24-15: Capacitive Loading Requirements on Output Pins300FIGURE 24-2: External Clock Timing301TABLE 24-16: External Clock Timing Requirements301TABLE 24-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)302TABLE 24-18: Auxiliary PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)302TABLE 24-19: AC Characteristics: Internal FRC Accuracy303TABLE 24-20: AC Characteristics: Internal LPRC Accuracy303FIGURE 24-3: I/O Timing Characteristics304TABLE 24-21: I/O Timing Requirements304FIGURE 24-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics305TABLE 24-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements306FIGURE 24-5: Timer1, 2 and 3 External Clock Timing Characteristics307TABLE 24-23: Timer1 External Clock Timing Requirements(1)307TABLE 24-24: Timer2 External Clock Timing Requirements308TABLE 24-25: Timer3 External Clock Timing Requirements308FIGURE 24-6: Input Capture x (ICx) Timing Characteristics309TABLE 24-26: Input Capture x Timing Requirements309FIGURE 24-7: Output Compare x Module (OCx) Timing Characteristics309TABLE 24-27: Output Compare x Module Timing Requirements309FIGURE 24-8: OCx/PWMx Module Timing Characteristics310TABLE 24-28: Simple OCx/PWMx MODE Timing Requirements310FIGURE 24-9: High-Speed PWMx Module Fault Timing Characteristics311FIGURE 24-10: High-Speed PWMx Module Timing Characteristics311TABLE 24-29: High-Speed PWMx Module Timing Requirements311TABLE 24-30: SPIx Maximum Data/Clock Rate Summary312FIGURE 24-11: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS312FIGURE 24-12: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS312TABLE 24-31: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements313FIGURE 24-13: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS314TABLE 24-32: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements314FIGURE 24-14: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS315TABLE 24-33: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements315FIGURE 24-15: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS316TABLE 24-34: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements317FIGURE 24-16: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS318TABLE 24-35: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements319FIGURE 24-17: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS320TABLE 24-36: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements321FIGURE 24-18: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS322TABLE 24-37: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements323FIGURE 24-19: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)324FIGURE 24-20: I2Cx Bus Data Timing Characteristics (Master Mode)324TABLE 24-38: I2Cx Bus Data Timing Requirements (Master Mode)325FIGURE 24-21: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)326FIGURE 24-22: I2Cx Bus Data Timing Characteristics (Slave Mode)326TABLE 24-39: I2Cx Bus Data Timing Requirements (Slave Mode)327TABLE 24-40: 10-bit High-speed ADC Module Specifications328TABLE 24-41: 10-bit, High-Speed ADC Module Timing Requirements329FIGURE 24-23: Analog-to-Digital Conversion Timing Per Input329TABLE 24-42: Comparator Module Specifications330TABLE 24-43: DAC Module Specifications330TABLE 24-44: DAC Output Buffer DC Specifications33125.0 High-Temperature Electrical Characteristics333Absolute Maximum Ratings(1)33325.1 High-Temperature DC Characteristics334TABLE 25-1: Operating MIPS vs. Voltage334TABLE 25-2: Thermal Operating Conditions334TABLE 25-3: DC Temperature and Voltage Specifications334TABLE 25-4: DC Characteristics: Power-down Current (Ipd)335TABLE 25-5: DC Characteristics: I/O Pin Output Specifications336TABLE 25-6: DC Characteristics: Program Memory33725.2 AC Characteristics and Timing Parameters338TABLE 25-7: Temperature and Voltage Specifications – AC338FIGURE 25-1: Load Conditions for Device Timing Specifications338TABLE 25-8: PLL Clock Timing Specifications338TABLE 25-9: SPIx Master Mode (cke = 0) Timing Requirements339TABLE 25-10: SPIx Module Master Mode (cke = 1) Timing Requirements339TABLE 25-11: SPIx Module Slave Mode (cke = 0) Timing Requirements340TABLE 25-12: SPIx Module Slave Mode (cke = 1) Timing Requirements34026.0 50 MIPS Electrical Characteristics341TABLE 26-1: Operating MIPS vs. Voltage342TABLE 26-2: DC Characteristics: Operating Current (Idd)342TABLE 26-3: DC Characteristics: Idle Current (Iidle)343TABLE 26-4: DC Characteristics: doze Current (Idoze)(1)344TABLE 26-5: External Clock Timing Requirements345TABLE 26-6: Simple OCx/PWMx MODE Timing Requirements34527.0 DC and AC Device Characteristics Graphs347FIGURE 27-1: Voh – 4x Driver Pins347FIGURE 27-2: Voh – 8x Driver Pins347FIGURE 27-3: Voh – 16x Driver Pins347FIGURE 27-4: Vol – 4x Driver Pins348FIGURE 27-5: Vol – 8x Driver Pins348FIGURE 27-6: Vol – 16x Driver Pins348FIGURE 27-7: Typical Ipd Current @ Vdd = 3.3V349FIGURE 27-8: Typical Idd Current @ Vdd = 3.3V349FIGURE 27-9: Typical Idoze Current @ Vdd = 3.3V349FIGURE 27-10: Typical Iidle Current @ Vdd = 3.3V349FIGURE 27-11: Typical FRC Frequency @ Vdd = 3.3V350FIGURE 27-12: Typical LPRC Frequency @ Vdd = 3.3V350FIGURE 27-13: Typical INTREF @ Vdd = 3.3V35028.0 Packaging Information35128.1 Package Marking Information35128.1 Package Marking Information (Continued)35228.2 Package Details353Appendix A: Revision History373Revision A (January 2008)373Revision B (June 2008)373TABLE A-1: Major Section Updates373Revision C and D (March 2009)377TABLE A-2: Major Section Updates377Revision E (December 2009)380TABLE A-3: Major Section Updates380Revision F (January 2012)382TABLE A-4: Major Section Updates382Revision G (May 2014)385INDEX387The Microchip Web Site393Customer Change Notification Service393Customer Support393Product Identification System395Worldwide Sales and Service398Tamanho: 4 MBPáginas: 398Language: EnglishAbrir o manual