用户手册 — Microchip Technology MA330020

目录

• Operating Conditions

  1
• Core: 16-Bit dsPIC33F CPU

  1
• Clock Management

  1
• Power Management

  1
• High-Speed PWM

  1
• Advanced Analog Features

  1
• Advanced Analog Features (Continued)

  1
• Timers/Output Compare/Input Capture

  1
• Communication Interfaces

  1
• Input/Output

  1
• Qualification and Class B Support

  1
• Debugger Development Support

  1
• dsPIC33FJ06GS101/X02 AND dsPIC33FJ16GSX02/X04 Product Families

  2
  • TABLE 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families

    2
  • Pin Diagrams

    3
  • Pin Diagrams (Continued)

    4
  • Pin Diagrams (Continued)

    5
  • Pin Diagrams (Continued)

    6
  • Pin Diagrams (Continued)

    7
  • Pin Diagrams (Continued)

    8
  • Pin Diagrams (Continued)

    9
  • Pin Diagrams (Continued)

    10
  • Pin Diagrams (Continued)

    11
  • Pin Diagrams (Continued)

    12
  • Table of Contents

    13
  • Most Current Data Sheet

    14
  • Errata

    14
  • Customer Notification System

    14
  • Referenced Sources

    15
• 1.0 Device Overview

  17
  • FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Block Diagram

    18
  • TABLE 1-1: Pinout I/O Descriptions

    19
• 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers

  21
  • 2.1 Basic Connection Requirements

    21
  • 2.2 Decoupling Capacitors

    21
    • FIGURE 2-1: Recommended Minimum Connection

      22
    • 2.2.1 Tank Capacitors

      22
  • 2.3 Capacitor on Internal Voltage Regulator (Vcap)

    22
  • 2.4 Master Clear (MCLR) Pin

    22
    • FIGURE 2-2: Example of MCLR Pin Connections

      22
  • 2.5 ICSP™ Pins

    23
  • 2.6 External Oscillator Pins

    23
    • FIGURE 2-3: Suggested Placement of the Oscillator Circuit

      23
  • 2.7 Oscillator Value Conditions on Device Start-up

    23
  • 2.8 Configuration of Analog and Digital Pins During ICSP Operations

    24
  • 2.9 Unused I/Os

    24
  • 2.10 Typical Application Connection Examples

    24
    • FIGURE 2-4: Digital PFC

      25
    • FIGURE 2-5: boost Converter Implementation

      25
    • FIGURE 2-6: Single-Phase Synchronous Buck converter

      26
    • FIGURE 2-7: Multi-Phase Synchronous Buck converter

      26
    • FIGURE 2-8: Off-Line UPS

      27
    • FIGURE 2-9: interleaved PFC

      28
    • FIGURE 2-10: Phase-Shifted Full-Bridge Converter

      29
    • FIGURE 2-11: AC-to-DC Power Supply with PFC and Three Outputs (12V, 5V and 3.3V)

      30
• 3.0 CPU

  31
  • 3.1 Data Addressing Overview

    31
  • 3.2 DSP Engine Overview

    31
  • 3.3 Special MCU Features

    32
    • FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU Core Block Diagram

      32
    • FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Programmer’s Model

      33
  • 3.4 CPU Control Registers

    34
    • Register 3-1: SR: CPU STATUS Register

      34
    • Register 3-2: CORCON: CORE Control Register

      36
  • 3.5 Arithmetic Logic Unit (ALU)

    38
    • 3.5.1 Multiplier

      38
    • 3.5.2 Divider

      38
  • 3.6 DSP Engine

    38
    • TABLE 3-1: DSP Instructions Summary

      38
    • FIGURE 3-3: DSP Engine Block Diagram

      39
    • 3.6.1 Multiplier

      40
    • 3.6.2 Data Accumulators and Adder/Subtracter

      40
    • 3.6.3 Accumulator ‘Write Back’

      41
    • 3.6.4 Barrel Shifter

      42
• 4.0 Memory Organization

  43
  • 4.1 Program Address Space

    43
    • FIGURE 4-1: Program Memory Maps for dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Devices

      43
    • 4.1.1 Program Memory Organization

      44
    • 4.1.2 Interrupt and Trap Vectors

      44
      • FIGURE 4-2: Program Memory Organization

        44
  • 4.2 Data Address Space

    45
    • 4.2.1 Data Space Width

      45
    • 4.2.2 Data Memory Organization and Alignment

      45
    • 4.2.3 SFR Space

      45
    • 4.2.4 Near Data Space

      45
      • FIGURE 4-3: Data Memory Map for dsPIC33FJ06GS101/102 Devices with 256 bytes of RAM

        46
      • FIGURE 4-4: Data Memory Map for dsPIC33FJ06GS202 Device with 1-Kbyte RAM

        47
      • FIGURE 4-5: Data Memory Map for dsPIC33FJ16GS402/404/502/504 Devices with 2-KBYTE RAM

        48
    • 4.2.5 X and Y Data Spaces

      49
      • TABLE 4-1: CPU Core Register Map

        50
      • TABLE 4-2: Change Notification Register Map for dsPIC33FJ06GS101

        51
      • TABLE 4-3: Change Notification Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS502

        51
      • TABLE 4-4: Change Notification Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS504

        51
      • TABLE 4-5: Interrupt Controller Register Map for dsPIC33FJ06GS101 Devices Only

        52
      • TABLE 4-6: Interrupt Controller Register Map for dsPIC33FJ06GS102 Devices Only

        53
      • TABLE 4-7: Interrupt Controller Register Map for dsPIC33FJ06G202 Devices Only

        54
      • TABLE 4-8: Interrupt Controller Register Map for dsPIC33FJ16GS402/404 Devices Only

        55
      • TABLE 4-9: Interrupt Controller Register Map for dsPIC33FJ16GS502 Devices Only

        56
      • TABLE 4-10: Interrupt Controller Register Map for dsPIC33FJ16GS504 Devices Only

        57
      • TABLE 4-11: Timer Register Map for dsPIC33FJ06GS101 and dsPIC33FJ06GSx02

        58
      • TABLE 4-12: Timer Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ16GSX04

        58
      • TABLE 4-13: Input Capture Register Map for dsPIC33FJ06GS202

        58
      • TABLE 4-14: Input Capture Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ16GSX04

        59
      • TABLE 4-15: Output Compare Register Map for dsPIC33FJ06GS101 and dsPIC33FJ06GSX02

        59
      • TABLE 4-16: Output Compare Register Map for dsPIC33FJ16GSX02 and dsPIC33FJ06GSX04

        59
      • TABLE 4-17: High-Speed PWM Register Map

        59
      • TABLE 4-18: High-Speed PWM Generator 1 Register Map

        60
      • TABLE 4-19: High-Speed PWM Generator 2 Register Map for dsPIC33FJ06GS102/202 and dsPIC33FJ16GSX02/X04 Devices Only

        60
      • TABLE 4-20: High-Speed PWM Generator 3 Register Map for dsPIC33FJ16GSX02/X04 Devices Only

        61
      • TABLE 4-21: High-Speed PWM Generator 4 Register Map for dsPIC33FJ06GS101 and dsPIC33FJ16GS50X Devices Only

        61
      • TABLE 4-22: I2C1 Register Map

        62
      • TABLE 4-23: UART1 Register Map

        62
      • TABLE 4-24: SPI1 Register Map

        62
      • TABLE 4-25: High-Speed 10-Bit ADC Register Map for dsPIC33FJ06GS101 devices Only

        63
      • TABLE 4-26: High-Speed 10-Bit ADC Register Map for dsPIC33FJ06GS102 Devices Only

        63
      • TABLE 4-27: High-Speed 10-bit ADC Register Map for dsPIC33FJ06GS202 Devices Only

        64
      • TABLE 4-28: High-Speed 10-bit ADC Register Map for dsPIC33FJ16GS402/404 Devices Only

        64
      • TABLE 4-29: High-Speed 10-bit ADC Register Map for dsPIC33FJ16GS502 Devices Only

        65
      • TABLE 4-30: High-Speed 10-Bit ADC Register Map for dsPIC33FJ16GS504 Devices Only

        66
      • TABLE 4-31: Analog Comparator Control Register Map for dsPIC33FJ06GS202 Devices Only

        67
      • TABLE 4-32: Analog Comparator Control Register Map dsPIC33FJ16GS502/504 Devices Only

        67
      • TABLE 4-33: Peripheral Pin Select Input Register Map

        68
      • TABLE 4-34: Peripheral Pin Select Output Register Map for dsPIC33FJ06GS101

        68
      • TABLE 4-35: Peripheral Pin Select Output Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 and dsPIC33FJ16GS502

        69
      • TABLE 4-36: Peripheral Pin Select Output Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS504

        69
      • TABLE 4-37: PORTA Register Map

        70
      • TABLE 4-38: PORTB Register Map for dsPIC33FJ06GS101

        70
      • TABLE 4-39: PORTB Register Map for dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402, dsPIC33FJ16GS404, dsPIC33FJ16GS502 and dsPIC33FJ16GS504

        70
      • TABLE 4-40: PORTC Register Map for dsPIC33FJ16GS404 and dsPIC33FJ16GS504

        70
      • TABLE 4-41: System Control Register Map

        71
      • TABLE 4-42: NVM Register Map

        71
      • TABLE 4-43: PMD Register Map for dsPIC33FJ06GS101 Devices Only

        71
      • TABLE 4-44: PMD Register Map for dsPIC33FJ06GS102 Devices Only

        71
      • TABLE 4-45: PMD REGISTER MAP for dsPIC33FJ06GS202 Devices Only

        72
      • TABLE 4-46: PMD Register Map for dsPIC33FJ16GS402 and dsPIC33FJ16GS404 Devices Only

        72
      • TABLE 4-47: PMD Register Map for dsPIC33FJ16GS502 and dsPIC33FJ16GS504 Devices Only

        72
    • 4.2.6 Software Stack

      73
      • FIGURE 4-6: CALL Stack Frame

        73
  • 4.3 Instruction Addressing Modes

    73
    • 4.3.1 File Register Instructions

      73
    • 4.3.2 MCU Instructions

      73
      • TABLE 4-48: Fundamental Addressing Modes Supported

        74
    • 4.3.3 Move and Accumulator Instructions

      74
    • 4.3.4 MAC Instructions

      74
    • 4.3.5 Other Instructions

      74
  • 4.4 Modulo Addressing

    75
    • 4.4.1 Start and End Address

      75
    • 4.4.2 W Address Register Selection

      75
      • FIGURE 4-7: Modulo Addressing Operation Example

        75
    • 4.4.3 Modulo Addressing Applicability

      76
  • 4.5 Bit-Reversed Addressing

    76
    • 4.5.1 Bit-Reversed Addressing Implementation

      76
      • FIGURE 4-8: Bit-Reversed Address Example

        77
      • TABLE 4-49: Bit-Reversed Address Sequence (16-Entry)

        77
  • 4.6 Interfacing Program and Data Memory Spaces

    78
    • 4.6.1 Addressing Program Space

      78
      • TABLE 4-50: Program Space Address Construction

        78
      • FIGURE 4-9: Data Access from Program Space Address Generation

        79
    • 4.6.2 Data Access from Program Memory Using Table Instructions

      80
      • FIGURE 4-10: Accessing Program Memory with Table Instructions

        80
    • 4.6.3 Reading Data from Program Memory Using Program Space Visibility

      81
      • FIGURE 4-11: Program Space Visibility Operation

        81
• 5.0 Flash Program Memory

  83
  • 5.1 Table Instructions and Flash Programming

    83
    • FIGURE 5-1: Addressing for Table Registers

      83
  • 5.2 RTSP Operation

    84
  • 5.3 Programming Operations

    84
    • EQUATION 5-1: Programming Time

      84
    • EQUATION 5-2: Minimum Row Write Time

      84
    • EQUATION 5-3: Maximum Row Write Time

      84
  • 5.4 Control Registers

    84
    • Register 5-1: NVMCON: Flash Memory Control Register

      85
    • Register 5-2: NVMKEY: Nonvolatile Memory Key Register

      86
    • 5.4.1 Programming Algorithm for Flash Program Memory

      87
      • EXAMPLE 5-1: Erasing a Program Memory Page

        87
      • EXAMPLE 5-2: Loading the Write Buffers

        88
      • EXAMPLE 5-3: Initiating a Programming Sequence

        88
• 6.0 Resets

  89
  • FIGURE 6-1: Reset System Block Diagram

    89
  • Register 6-1: RCON: Reset Control Register(1)

    90
  • 6.1 System Reset

    92
    • TABLE 6-1: Oscillator Delay

      92
    • FIGURE 6-2: System Reset Timing

      93
    • TABLE 6-2: Oscillator Delay

      93
  • 6.2 Power-on Reset (POR)

    94
  • 6.2.1 Brown-out Reset (BOR) and Power-up Timer (PWRT)

    94
    • FIGURE 6-3: Brown-out Situations

      94
  • 6.3 External Reset (EXTR)

    95
    • 6.3.0.1 External Supervisory Circuit

      95
    • 6.3.0.2 Internal Supervisory Circuit

      95
  • 6.4 Software RESET Instruction (SWR)

    95
  • 6.5 Watchdog Timer Time-out Reset (WDTO)

    95
  • 6.6 Trap Conflict Reset

    95
  • 6.7 Configuration Mismatch Reset

    95
  • 6.8 Illegal Condition Device Reset

    95
    • 6.8.1 Illegal Opcode Reset

      95
    • 6.8.2 Uninitialized W Register Reset

      96
    • 6.8.3 Security Reset

      96
  • 6.9 Using the RCON Status Bits

    96
    • TABLE 6-3: Reset Flag Bit Operation

      96
• 7.0 Interrupt Controller

  97
  • 7.1 Interrupt Vector Table

    97
    • 7.1.1 Alternate Interrupt Vector Table

      97
  • 7.2 Reset Sequence

    97
    • FIGURE 7-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Interrupt Vector Table

      98
    • TABLE 7-1: Interrupt Vectors

      99
  • 7.3 Interrupt Control and Status Registers

    100
    • 7.3.1 INTCON1 and INTCON2

      100
    • 7.3.2 IFSx

      100
    • 7.3.3 IECx

      100
    • 7.3.4 IPCx

      100
    • 7.3.5 INTTREG

      100
    • 7.3.6 Status/Control Registers

      100
      • Register 7-1: SR: CPU STATUS Register(1)

        101
      • Register 7-2: CORCON: CORE Control Register(1)

        101
      • Register 7-3: INTCON1: Interrupt Control Register 1

        102
      • Register 7-4: INTCON2: Interrupt Control Register 2

        104
      • Register 7-5: IFS0: Interrupt Flag Status Register 0

        105
      • Register 7-6: IFS1: Interrupt Flag Status Register 1

        107
      • Register 7-7: IFS3: Interrupt Flag Status Register 3

        108
      • Register 7-8: IFS4: Interrupt Flag Status Register 4

        108
      • Register 7-9: IFS5: Interrupt Flag Status Register 5

        109
      • Register 7-10: IFS6: Interrupt Flag Status Register 6

        110
      • Register 7-11: IFS7: Interrupt Flag Status Register 7

        111
      • Register 7-12: IEC0: Interrupt Enable Control Register 0

        112
      • Register 7-13: IEC1: Interrupt Enable Control Register 1

        114
      • Register 7-14: IEC3: Interrupt Enable Control Register 3

        115
      • Register 7-15: IEC4: Interrupt Enable Control Register 4

        115
      • Register 7-16: IEC5: Interrupt Enable Control Register 5

        116
      • Register 7-17: IEC6: Interrupt Enable Control Register 6

        117
      • Register 7-18: IEC7: Interrupt Enable Control Register 7

        118
      • Register 7-19: IPC0: Interrupt Priority Control Register 0

        119
      • Register 7-20: IPC1: Interrupt Priority Control Register 1

        120
      • Register 7-21: IPC2: Interrupt Priority Control Register 2

        121
      • Register 7-22: IPC3: Interrupt Priority Control Register 3

        122
      • Register 7-23: IPC4: Interrupt Priority Control Register 4

        123
      • Register 7-24: IPC5: Interrupt Priority Control Register 5

        124
      • Register 7-25: IPC7: Interrupt Priority Control Register 7

        124
      • Register 7-26: IPC14: Interrupt Priority Control Register 14

        125
      • Register 7-27: IPC16: Interrupt Priority Control Register 16

        125
      • Register 7-28: IPC23: Interrupt Priority Control Register 23

        126
      • Register 7-29: IPC24: Interrupt Priority Control Register 24

        127
      • Register 7-30: IPC25: Interrupt Priority Control Register 25

        128
      • Register 7-31: IPC26: Interrupt Priority Control Register 26

        129
      • Register 7-32: IPC27: Interrupt Priority Control Register 27

        130
      • Register 7-33: IPC28: Interrupt Priority Control Register 28

        131
      • Register 7-34: IPC29: Interrupt Priority Control Register 29

        132
      • Register 7-35: INTTREG: Interrupt Control and Status Register

        133
  • 7.4 Interrupt Setup Procedures

    134
    • 7.4.1 Initialization

      134
    • 7.4.2 Interrupt Service Routine

      134
    • 7.4.3 Trap Service Routine

      134
    • 7.4.4 Interrupt Disable

      134
• 8.0 Oscillator Configuration

  135
  • FIGURE 8-1: Oscillator System Diagram

    135
  • 8.1 CPU Clocking System

    136
    • 8.1.1 System Clock Sources

      136
    • 8.1.2 System Clock Selection

      136
      • EQUATION 8-1: Device Operating Frequency

        136
      • TABLE 8-1: Configuration Bit Values for Clock Selection

        136
    • 8.1.3 PLL Configuration

      137
      • EQUATION 8-2: Fosc Calculation

        137
      • EQUATION 8-3: XT with PLL Mode Example

        137
      • FIGURE 8-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PLL Block Diagram

        137
  • 8.2 Auxiliary Clock Generation

    138
  • 8.3 Reference Clock Generation

    138
  • 8.4 Oscillator Control Registers

    139
    • Register 8-1: OSCCON: Oscillator Control Register(1,2)

      139
    • Register 8-2: CLKDIV: Clock Divisor Register(1)

      141
    • Register 8-3: PLLFBD: PLL Feedback Divisor Register(1)

      142
    • Register 8-4: OSCTUN: FRC Oscillator Tuning Register(1)

      143
    • Register 8-5: ACLKCON: Auxiliary Clock Divisor Control Register(1)

      144
    • Register 8-6: REFOCON: Reference Oscillator Control Register

      145
  • 8.5 Clock Switching Operation

    146
    • 8.5.1 Enabling Clock Switching

      146
    • 8.5.2 Oscillator Switching Sequence

      146
  • 8.6 Fail-Safe Clock Monitor (FSCM)

    146
• 9.0 Power-Saving Features

  147
  • 9.1 Clock Frequency and Clock Switching

    147
  • 9.2 Instruction-Based Power-Saving Modes

    147
    • 9.2.1 Sleep Mode

      147
      • EXAMPLE 9-1: PWRSAV Instruction Syntax

        147
    • 9.2.2 Idle Mode

      148
    • 9.2.3 Interrupts Coincident with Power Save Instructions

      148
  • 9.3 Doze Mode

    148
  • 9.4 Peripheral Module Disable

    148
    • Register 9-1: PMD1: Peripheral Module Disable Control Register 1

      149
    • Register 9-2: PMD2: Peripheral Module Disable Control Register 2

      150
    • Register 9-3: PMD3: Peripheral Module Disable Control Register 3

      151
    • Register 9-4: PMD4: Peripheral Module Disable Control Register 4

      151
    • Register 9-5: PMD6: Peripheral Module Disable Control Register 6

      152
    • Register 9-6: PMD7: Peripheral Module Disable Control Register 7

      153
• 10.0 I/O Ports

  155
  • 10.1 Parallel I/O (PIO) Ports

    155
    • FIGURE 10-1: Block Diagram of a Typical Shared Port Structure

      155
  • 10.2 Open-Drain Configuration

    156
  • 10.3 Configuring Analog Port Pins

    156
  • 10.4 I/O Port Write/Read Timing

    156
  • 10.5 Input Change Notification

    156
    • EQUATION 10-1: Port Write/Read Example

      156
  • 10.6 Peripheral Pin Select

    157
    • 10.6.1 Available Pins

      157
    • 10.6.2 Controlling Peripheral Pin Select

      157
      • FIGURE 10-2: Remappable MUX Input for U1RX

        157
      • TABLE 10-1: Selectable Input Sources (Maps Input To Function)

        158
      • FIGURE 10-3: Multiplexing of Remappable Output for RPn

        159
      • TABLE 10-2: Output Selection for Remappable Pin (RPn)

        159
    • 10.6.3 Controlling Configuration Changes

      160
  • 10.7 Peripheral Pin Select Registers

    161
    • Register 10-1: RPINR0: Peripheral Pin Select Input Register 0

      161
    • Register 10-2: RPINR1: Peripheral Pin Select Input Register 1

      162
    • Register 10-3: RPINR3: Peripheral Pin Select Input Register 3

      163
    • Register 10-4: RPINR7: Peripheral Pin Select Input Register 7

      164
    • Register 10-5: RPINR11: Peripheral Pin Select Input Register 11

      165
    • Register 10-6: RPINR18: Peripheral Pin Select Input Register 18

      166
    • Register 10-7: RPINR20: Peripheral Pin Select Input Register 20

      167
    • Register 10-8: RPINR21: Peripheral Pin Select Input Register 21

      168
    • Register 10-9: RPINR29: Peripheral Pin Select Input Register 29

      169
    • Register 10-10: RPINR30: Peripheral Pin Select Input Register 30

      170
    • Register 10-11: RPINR31: Peripheral Pin Select Input Register 31

      171
    • Register 10-12: RPINR32: Peripheral Pin Select Input Register 32

      172
    • Register 10-13: RPINR33: Peripheral Pin Select Input Register 33

      173
    • Register 10-14: RPINR34: Peripheral Pin Select Input Register 34

      174
    • Register 10-15: RPOR0: Peripheral Pin Select Output Register 0

      174
    • Register 10-16: RPOR1: Peripheral Pin Select Output Register 1

      175
    • Register 10-17: RPOR2: Peripheral Pin Select Output Register 2

      175
    • Register 10-18: RPOR3: Peripheral Pin Select Output Register 3

      176
    • Register 10-19: RPOR4: Peripheral Pin Select Output Register 4(1)

      176
    • Register 10-20: RPOR5: Peripheral Pin Select Output Register 5(1)

      177
    • Register 10-21: RPOR6: Peripheral Pin Select Output Register 6(1)

      177
    • Register 10-22: RPOR7: Peripheral Pin Select Output Register 7(1)

      178
    • Register 10-23: RPOR8: Peripheral Pin Select Output Register 8(1)

      178
    • Register 10-24: RPOR9: Peripheral Pin Select Output Register 9(1)

      179
    • Register 10-25: RPOR10: Peripheral Pin Select Output Register 10(1)

      179
    • Register 10-26: RPOR11: Peripheral Pin Select Output Register 11(1)

      180
    • Register 10-27: RPOR12: Peripheral Pin Select Output Register 12(1)

      180
    • Register 10-28: RPOR13: Peripheral Pin Select Output Register 13(1)

      181
    • Register 10-29: RPOR14: Peripheral Pin Select Output Register 14(1)

      181
    • Register 10-30: RPOR16: Peripheral Pin Select Output Register 16

      182
    • Register 10-31: RPOR17: Peripheral Pin Select Output Register 17

      182
• 11.0 Timer1

  183
  • TABLE 11-1: Timer Mode Settings

    183
  • FIGURE 11-1: 16-bit Timer1 Module Block Diagram

    183
  • Register 11-1: T1CON: Timer1 Control Register

    184
• 12.0 Timer2/3 Features

  185
  • FIGURE 12-1: Type B Timer Block Diagram (x = 2)

    185
  • FIGURE 12-2: Type C Timer Block Diagram (X = 3)

    185
  • TABLE 12-1: Timer Mode Settings

    186
  • 12.1 16-Bit Operation

    186
  • 12.2 32-Bit Operation

    186
    • TABLE 12-2: 32-bit Timer

      186
    • FIGURE 12-3: 32-Bit Timer Block Diagram

      187
    • Register 12-1: TxCON: Timerx Control Register (x = 2)

      188
    • Register 12-2: TyCON: Timery Control Register (y = 3)

      189
• 13.0 Input Capture

  191
  • FIGURE 13-1: Input Capture x Block Diagram

    191
  • 13.1 Input Capture Register

    192
    • Register 13-1: ICxCON: Input Capture x Control Register (x = 1, 2)

      192
• 14.0 Output Compare

  193
  • FIGURE 14-1: Output Compare x Module Block Diagram

    193
  • 14.1 Output Compare Modes

    194
    • TABLE 14-1: Output Compare Modes

      194
    • FIGURE 14-2: Output Compare Operation

      194
    • Register 14-1: OCxCON: Output Compare x Control Register (x = 1, 2)

      195
• 15.0 High-Speed PWM

  197
  • 15.1 Features Overview

    197
  • 15.2 Feature Description

    198
    • FIGURE 15-1: Simplified Conceptual Block Diagram of High-Speed PWM

      199
    • FIGURE 15-2: Partitioned Output Pair, Complementary PWM Mode

      200
  • 15.3 Control Registers

    200
    • Register 15-1: PTCON: PWM Time Base Control Register

      201
    • Register 15-2: PTCON2: PWM Clock Divider Select Register

      203
    • Register 15-3: PTPER: PWM Master Time Base Register(1)

      203
    • Register 15-4: SEVTCMP: PWM Special Event Compare Register

      204
    • Register 15-5: MDC: PWM Master Duty Cycle Register(1,2)

      204
    • Register 15-6: PWMCONx: PWMx Control Register

      205
    • Register 15-7: PDCx: PWMx Generator Duty Cycle Register(1,2)

      207
    • Register 15-8: SDCx: PWMx Secondary Duty Cycle Register(1,2)

      207
    • Register 15-9: PHASEx: PWMx Primary Phase-Shift Register(1,2)

      208
    • Register 15-10: SPHASEx: PWMx Secondary Phase-Shift Register(1,2)

      209
    • Register 15-11: DTRx: PWMx Dead-Time Register

      210
    • Register 15-12: ALTDTRx: PWMx Alternate Dead-Time Register

      210
    • Register 15-13: TRGCONx: PWMx Trigger Control Register

      211
    • Register 15-14: IOCONx: PWMx I/O Control Register

      212
    • Register 15-15: FCLCONx: PWMx Fault Current-Limit Control Register

      214
    • Register 15-16: TRIGx: PWMx Primary Trigger Compare Value Register

      216
    • Register 15-17: STRIGx: PWMx Secondary Trigger Compare Value Register

      216
    • Register 15-18: LEBCONx: Leading-Edge Blanking Control Register(1)

      217
    • Register 15-19: PWMCAPx: Primary PWMx Time Base Capture Register

      218
• 16.0 Serial Peripheral Interface (SPI)

  219
  • FIGURE 16-1: SPIx Module Block Diagram

    219
  • Register 16-1: SPIxSTAT: SPIx Status and Control Register

    220
  • Register 16-2: SPIxCON1: SPIx Control Register 1

    221
  • Register 16-3: SPIxCON2: SPIx Control Register 2

    223
• 17.0 Inter-Integrated Circuit (I2C™)

  225
  • 17.1 Operating Modes

    225
    • FIGURE 17-1: I2Cx Block Diagram (x = 1)

      226
  • 17.2 I2C Registers

    227
    • Register 17-1: I2CxCON: I2Cx Control Register

      228
    • Register 17-2: I2CxSTAT: I2Cx Status Register

      230
    • Register 17-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      232
• 18.0 Universal Asynchronous Receiver Transmitter (UART)

  233
  • Register 18-1: UxMODE: UARTx Mode Register

    234
  • Register 18-2: UxSTA: UARTx Status and Control Register

    236
• 19.0 High-Speed 10-bit Analog-to-Digital Converter (ADC)

  239
  • 19.1 Features Overview

    239
  • 19.2 Module Description

    239
  • 19.3 Module Functionality

    239
    • FIGURE 19-1: ADC Block Diagram for dsPIC33FJ06GS101 Devices with One SAR

      240
    • FIGURE 19-2: ADC Block Diagram for dsPIC33FJ06GS102 Devices with One SAR

      241
    • FIGURE 19-3: ADC Block Diagram for dsPIC33FJ06GS202 Devices with One SAR

      242
    • FIGURE 19-4: ADC Block Diagram for dsPIC33FJ16GS402/404 Devices with One SAR

      243
    • FIGURE 19-5: ADC Block Diagram for dsPIC33FJ16GS502 Devices with Two SARS

      244
    • FIGURE 19-6: ADC Block Diagram for dsPIC33FJ16GS504 devices with two SARs

      245
  • 19.4 ADC Control Registers

    246
    • Register 19-1: ADCON: Analog-to-Digital Control Register

      247
    • Register 19-2: ADSTAT: Analog-to-Digital Status Register

      249
    • Register 19-3: ADBASE: Analog-to-Digital Base Register(1,2)

      250
    • Register 19-4: ADPCFG: Analog-to-Digital Port Configuration Register

      250
    • Register 19-5: ADCPC0: Analog-to-Digital Convert Pair Control Register 0

      251
    • Register 19-6: ADCPC1: Analog-to-Digital Convert Pair Control Register 1

      254
    • Register 19-7: ADCPC2: Analog-to-Digital Convert Pair Control Register 2(1)

      257
    • Register 19-8: ADCPC3: Analog-to-Digital Convert Pair Control Register 3(1)

      260
• 20.0 High-Speed Analog Comparator

  263
  • 20.1 Features Overview

    263
  • 20.2 Module Description

    263
    • FIGURE 20-1: High-Speed Analog Comparator Module Block Diagram

      263
  • 20.3 Module Applications

    264
  • 20.4 DAC

    264
  • 20.5 Interaction with I/O Buffers

    264
  • 20.6 Digital Logic

    264
  • 20.7 Comparator Input Range

    264
  • 20.8 DAC Output Range

    264
  • 20.9 Comparator Registers

    264
    • Register 20-1: CMPCONx: Comparator Control x Register

      265
    • Register 20-2: CMPDACx: Comparator DAC x Control Register

      266
• 21.0 Special Features

  267
  • 21.1 Configuration Bits

    267
    • TABLE 21-1: Device Configuration Register Map

      267
    • TABLE 21-2: dsPIC33F Configuration Bits Description

      268
  • 21.2 On-Chip Voltage Regulator

    270
    • FIGURE 21-1: Connections for the On-Chip Voltage Regulator(1,2,3)

      270
  • 21.3 BOR: Brown-out Reset

    270
  • 21.4 Watchdog Timer (WDT)

    271
    • 21.4.1 Prescaler/Postscaler

      271
    • 21.4.2 Sleep and Idle Modes

      271
    • 21.4.3 Enabling WDT

      271
      • FIGURE 21-2: WDT Block diagram

        271
  • 21.5 JTAG Interface

    272
  • 21.6 In-Circuit Serial Programming

    272
  • 21.7 In-Circuit Debugger

    272
  • 21.8 Code Protection and CodeGuard™ Security

    273
    • TABLE 21-3: Code Flash Security Segment Sizes for 6-Kbyte Devices

      273
    • TABLE 21-4: Code Flash Security Segment Sizes for 16-Kbyte Devices

      273
• 22.0 Instruction Set Summary

  275
  • TABLE 22-1: Symbols Used in Opcode Descriptions

    276
  • TABLE 22-2: Instruction Set Overview

    278
• 23.0 Development Support

  283
  • 23.1 MPLAB X Integrated Development Environment Software

    283
  • 23.2 MPLAB XC Compilers

    284
  • 23.3 MPASM Assembler

    284
  • 23.4 MPLINK Object Linker/ MPLIB Object Librarian

    284
  • 23.5 MPLAB Assembler, Linker and Librarian for Various Device Families

    284
  • 23.6 MPLAB X SIM Software Simulator

    285
  • 23.7 MPLAB REAL ICE In-Circuit Emulator System

    285
  • 23.8 MPLAB ICD 3 In-Circuit Debugger System

    285
  • 23.9 PICkit 3 In-Circuit Debugger/ Programmer

    285
  • 23.10 MPLAB PM3 Device Programmer

    285
  • 23.11 Demonstration/Development Boards, Evaluation Kits and Starter Kits

    286
  • 23.12 Third-Party Development Tools

    286
• 24.0 Electrical Characteristics

  287
  • Absolute Maximum Ratings(1)

    287
  • 24.1 DC Characteristics

    288
    • TABLE 24-1: Operating MIPS vs. Voltage

      288
    • TABLE 24-2: Thermal Operating Conditions

      288
    • TABLE 24-3: Thermal Packaging Characteristics

      288
    • TABLE 24-4: DC Temperature and Voltage specifications

      289
    • TABLE 24-5: DC Characteristics: Operating Current (Idd)

      290
    • TABLE 24-6: DC Characteristics: Idle Current (Iidle)

      292
    • TABLE 24-7: DC Characteristics: Power-Down Current (Ipd)

      293
    • TABLE 24-8: DC Characteristics: Doze Current (Idoze)

      294
    • TABLE 24-9: DC Characteristics: I/O Pin Input Specifications

      295
    • TABLE 24-10: DC Characteristics: I/O Pin Output Specifications

      297
    • TABLE 24-11: Electrical Characteristics: BOR

      298
    • TABLE 24-12: DC Characteristics: Program Memory

      299
    • TABLE 24-13: Internal Voltage Regulator Specifications

      299
  • 24.2 AC Characteristics and Timing Parameters

    300
    • TABLE 24-14: Temperature and Voltage Specifications – AC

      300
    • FIGURE 24-1: Load Conditions for Device Timing Specifications

      300
    • TABLE 24-15: Capacitive Loading Requirements on Output Pins

      300
    • FIGURE 24-2: External Clock Timing

      301
    • TABLE 24-16: External Clock Timing Requirements

      301
    • TABLE 24-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      302
    • TABLE 24-18: Auxiliary PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      302
    • TABLE 24-19: AC Characteristics: Internal FRC Accuracy

      303
    • TABLE 24-20: AC Characteristics: Internal LPRC Accuracy

      303
    • FIGURE 24-3: I/O Timing Characteristics

      304
    • TABLE 24-21: I/O Timing Requirements

      304
    • FIGURE 24-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics

      305
    • TABLE 24-22: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements

      306
    • FIGURE 24-5: Timer1, 2 and 3 External Clock Timing Characteristics

      307
    • TABLE 24-23: Timer1 External Clock Timing Requirements(1)

      307
    • TABLE 24-24: Timer2 External Clock Timing Requirements

      308
    • TABLE 24-25: Timer3 External Clock Timing Requirements

      308
    • FIGURE 24-6: Input Capture x (ICx) Timing Characteristics

      309
    • TABLE 24-26: Input Capture x Timing Requirements

      309
    • FIGURE 24-7: Output Compare x Module (OCx) Timing Characteristics

      309
    • TABLE 24-27: Output Compare x Module Timing Requirements

      309
    • FIGURE 24-8: OCx/PWMx Module Timing Characteristics

      310
    • TABLE 24-28: Simple OCx/PWMx MODE Timing Requirements

      310
    • FIGURE 24-9: High-Speed PWMx Module Fault Timing Characteristics

      311
    • FIGURE 24-10: High-Speed PWMx Module Timing Characteristics

      311
    • TABLE 24-29: High-Speed PWMx Module Timing Requirements

      311
    • TABLE 24-30: SPIx Maximum Data/Clock Rate Summary

      312
    • FIGURE 24-11: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 0) TIMING CHARACTERISTICS

      312
    • FIGURE 24-12: SPIx MASTER MODE (Half-Duplex, Transmit Only, CKE = 1) TIMING CHARACTERISTICS

      312
    • TABLE 24-31: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements

      313
    • FIGURE 24-13: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      314
    • TABLE 24-32: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements

      314
    • FIGURE 24-14: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS

      315
    • TABLE 24-33: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements

      315
    • FIGURE 24-15: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      316
    • TABLE 24-34: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements

      317
    • FIGURE 24-16: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      318
    • TABLE 24-35: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements

      319
    • FIGURE 24-17: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS

      320
    • TABLE 24-36: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements

      321
    • FIGURE 24-18: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS

      322
    • TABLE 24-37: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements

      323
    • FIGURE 24-19: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      324
    • FIGURE 24-20: I2Cx Bus Data Timing Characteristics (Master Mode)

      324
    • TABLE 24-38: I2Cx Bus Data Timing Requirements (Master Mode)

      325
    • FIGURE 24-21: I2Cx Bus Start/Stop Bits Timing Characteristics (Slave Mode)

      326
    • FIGURE 24-22: I2Cx Bus Data Timing Characteristics (Slave Mode)

      326
    • TABLE 24-39: I2Cx Bus Data Timing Requirements (Slave Mode)

      327
    • TABLE 24-40: 10-bit High-speed ADC Module Specifications

      328
    • TABLE 24-41: 10-bit, High-Speed ADC Module Timing Requirements

      329
    • FIGURE 24-23: Analog-to-Digital Conversion Timing Per Input

      329
    • TABLE 24-42: Comparator Module Specifications

      330
    • TABLE 24-43: DAC Module Specifications

      330
    • TABLE 24-44: DAC Output Buffer DC Specifications

      331
• 25.0 High-Temperature Electrical Characteristics

  333
  • Absolute Maximum Ratings(1)

    333
  • 25.1 High-Temperature DC Characteristics

    334
    • TABLE 25-1: Operating MIPS vs. Voltage

      334
    • TABLE 25-2: Thermal Operating Conditions

      334
    • TABLE 25-3: DC Temperature and Voltage Specifications

      334
    • TABLE 25-4: DC Characteristics: Power-down Current (Ipd)

      335
    • TABLE 25-5: DC Characteristics: I/O Pin Output Specifications

      336
    • TABLE 25-6: DC Characteristics: Program Memory

      337
  • 25.2 AC Characteristics and Timing Parameters

    338
    • TABLE 25-7: Temperature and Voltage Specifications – AC

      338
    • FIGURE 25-1: Load Conditions for Device Timing Specifications

      338
    • TABLE 25-8: PLL Clock Timing Specifications

      338
    • TABLE 25-9: SPIx Master Mode (cke = 0) Timing Requirements

      339
    • TABLE 25-10: SPIx Module Master Mode (cke = 1) Timing Requirements

      339
    • TABLE 25-11: SPIx Module Slave Mode (cke = 0) Timing Requirements

      340
    • TABLE 25-12: SPIx Module Slave Mode (cke = 1) Timing Requirements

      340
• 26.0 50 MIPS Electrical Characteristics

  341
  • TABLE 26-1: Operating MIPS vs. Voltage

    342
  • TABLE 26-2: DC Characteristics: Operating Current (Idd)

    342
  • TABLE 26-3: DC Characteristics: Idle Current (Iidle)

    343
  • TABLE 26-4: DC Characteristics: doze Current (Idoze)(1)

    344
  • TABLE 26-5: External Clock Timing Requirements

    345
  • TABLE 26-6: Simple OCx/PWMx MODE Timing Requirements

    345
• 27.0 DC and AC Device Characteristics Graphs

  347
  • FIGURE 27-1: Voh – 4x Driver Pins

    347
  • FIGURE 27-2: Voh – 8x Driver Pins

    347
  • FIGURE 27-3: Voh – 16x Driver Pins

    347
  • FIGURE 27-4: Vol – 4x Driver Pins

    348
  • FIGURE 27-5: Vol – 8x Driver Pins

    348
  • FIGURE 27-6: Vol – 16x Driver Pins

    348
  • FIGURE 27-7: Typical Ipd Current @ Vdd = 3.3V

    349
  • FIGURE 27-8: Typical Idd Current @ Vdd = 3.3V

    349
  • FIGURE 27-9: Typical Idoze Current @ Vdd = 3.3V

    349
  • FIGURE 27-10: Typical Iidle Current @ Vdd = 3.3V

    349
  • FIGURE 27-11: Typical FRC Frequency @ Vdd = 3.3V

    350
  • FIGURE 27-12: Typical LPRC Frequency @ Vdd = 3.3V

    350
  • FIGURE 27-13: Typical INTREF @ Vdd = 3.3V

    350
• 28.0 Packaging Information

  351
  • 28.1 Package Marking Information

    351
  • 28.1 Package Marking Information (Continued)

    352
  • 28.2 Package Details

    353
• Appendix A: Revision History

  373
  • Revision A (January 2008)

    373
  • Revision B (June 2008)

    373
    • TABLE A-1: Major Section Updates

      373
  • Revision C and D (March 2009)

    377
    • TABLE A-2: Major Section Updates

      377
  • Revision E (December 2009)

    380
    • TABLE A-3: Major Section Updates

      380
  • Revision F (January 2012)

    382
    • TABLE A-4: Major Section Updates

      382
  • Revision G (May 2014)

    385
• INDEX

  387
• The Microchip Web Site

  393
• Customer Change Notification Service

  393
• Customer Support

  393
• Product Identification System

  395
• Worldwide Sales and Service

  398