Manuais de utilizador para Motorola DSP56301

índice analítico

• Title Page

  1
  • Contents

    5
  • Figures

    11
  • Tables

    15
• Chapter1 Overview

  17
  • 1.1 Manual Organization

    17
  • 1.2 Manual Conventions

    18
  • 1.3 DSP56300 Core Features

    20
  • 1.4 DSP56300 Core Functional Blocks

    22
    • 1.4.1 Data ALU

      22
      • 1.4.1.1 Data ALU Registers

        23
      • 1.4.1.2 Multiplier-Accumulator (MAC)

        23
    • 1.4.2 Address Generation Unit (AGU)

      23
    • 1.4.3 Program Control Unit (PCU)

      24
    • 1.4.4 PLL and Clock Oscillator

      25
    • 1.4.5 JTAG TAP and OnCE Module

      25
    • 1.4.6 On-Chip Memory

      26
  • 1.5 Internal Buses

    26
  • 1.6 DMA

    27
  • 1.7 Peripherals

    28
    • 1.7.1 General-Purpose Input/Output (GPIO) signals

      28
    • 1.7.2 Host Interface (HI32)

      28
    • 1.7.3 Enhance Synchronous Serial Interface (ESSI)

      28
    • 1.7.4 Serial Communications Interface (SCI)

      29
    • 1.7.5 Triple Timer Module

      29
  • 1.8 Related Documents and Web Sites

    30
• Chapter2 Signals/Connections

  31
  • 2.1 Power

    34
  • 2.2 Ground

    34
  • 2.3 Clock

    35
  • 2.4 PLL

    35
  • 2.5 External Memory Expansion Port (Port A)

    36
    • 2.5.1 External Address Bus

      36
    • 2.5.2 External Data Bus

      36
    • 2.5.3 External Bus Control

      36
  • 2.6 Interrupt and Mode Control

    39
  • 2.7 Host Interface (HI32)

    40
  • 2.8 Enhanced Synchronous Serial Interface 0

    52
  • 2.9 Enhanced Synchronous Serial Interface 1

    55
  • 2.10 Serial Communications Interface (SCI)

    57
  • 2.11 Timers

    57
  • 2.12 JTAG and OnCE Interface

    59
• Chapter3 Memory Configuration

  61
  • 3.1 Program Memory Space

    61
    • 3.1.1 Internal Program Memory

      62
    • 3.1.2 Memory Switch Modes—Program Memory

      62
    • 3.1.3 Instruction Cache

      62
    • 3.1.4 Program Bootstrap ROM

      63
  • 3.2 X Data Memory Space

    63
    • 3.2.1 Internal X Data Memory

      63
    • 3.2.2 Memory Switch Modes—X Data Memory

      63
    • 3.2.3 Internal I/O Space—X Data Memory

      64
  • 3.3 Y Data Memory Space

    64
    • 3.3.1 Internal Y Data Memory

      64
    • 3.3.2 Memory Switch Modes—Y Data Memory

      64
    • 3.3.3 External I/O Space—Y Data Memory

      65
  • 3.4 Dynamic Memory Configuration Switching

    65
  • 3.5 Sixteen-Bit Compatibility Mode Configuration

    66
  • 3.6 Internal Memory Configuration Summary

    66
  • 3.7 Memory Maps

    67
• Chapter4 Core Configuration

  75
  • 4.1 Operating Modes

    76
  • 4.2 Bootstrap Program

    79
  • 4.3 Central Processor Unit (CPU) Registers

    80
    • 4.3.1 Status Register (SR)

      80
    • 4.3.2 Operating Mode Register (OMR)

      86
  • 4.4 Configuring Interrupts

    89
    • 4.4.1 Interrupt Priority Registers (IPRC and IPRP)

      90
    • 4.4.2 Interrupt Table Memory Map

      91
    • 4.4.3 Processing Interrupt Source Priorities Within an IPL

      93
  • 4.5 PLL Control Register (PCTL)

    95
  • 4.6 Bus Interface Unit (BIU) Registers

    96
    • 4.6.1 Bus Control Register

      96
    • 4.6.2 DRAM Control Register (DCR)

      98
    • 4.6.3 Address Attribute Registers (AAR[0–3])

      101
  • 4.7 DMA Control Registers 5–0 (DCR[5–0])

    103
  • 4.8 Device Identification Register (IDR)

    108
  • 4.9 JTAG Identification (ID) Register

    109
  • 4.10 JTAG Boundary Scan Register (BSR)

    109
• Chapter5 Programming the Peripherals

  111
  • 5.1 Peripheral Initialization Steps

    111
  • 5.2 Mapping the Control Registers

    112
  • 5.3 Data Transfer Methods

    112
    • 5.3.1 Polling

      112
    • 5.3.2 Interrupts

      113
    • 5.3.3 DMA

      114
    • 5.3.4 Advantages and Disadvantages

      114
  • 5.4 General-Purpose Input/Output (GPIO)

    114
    • 5.4.1 Port B Signals and Registers

      115
    • 5.4.2 Port C Signals and Registers

      116
    • 5.4.3 Port D Signals and Registers

      116
    • 5.4.4 Port E Signals and Registers

      116
    • 5.4.5 Triple Timer Signals and Registers

      117
• Chapter6 Host Interface (HI32)

  119
  • 6.1 Features

    119
  • 6.2 Overview

    122
  • 6.3 Data Transfer Paths

    124
    • 6.3.1 Host-to-DSP Data Path

      124
    • 6.3.2 DSP-To-Host Data Path

      125
  • 6.4 Reset States

    130
  • 6.5 DSP-Side Operating Modes

    130
    • 6.5.1 Terminate and Reset (DCTR[HM] = $0)

      131
    • 6.5.2 PCI Mode (DCTR[HM] = $1)

      131
    • 6.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes

      133
    • 6.5.4 GPIO Mode (DCTR[HM] = $4)

      134
    • 6.5.5 Self-Configuration Mode (DCTR[HM] = $5)

      134
  • 6.6 Host Port Pins

    136
  • 6.7 HI32 DSP-Side Programming Model

    140
    • 6.7.1 DSP Control Register (DCTR)

      141
    • 6.7.2 DSP PCI Control Register (DPCR)

      144
    • 6.7.3 DSP PCI Master Control Register (DPMC)

      148
    • 6.7.4 DSP PCI Address Register (DPAR)

      151
    • 6.7.5 DSP Status Register (DSR)

      153
    • 6.7.6 DSP PCI Status Register (DPSR)

      156
    • 6.7.7 DSP Receive Data FIFO (DRXR)

      159
    • 6.7.8 DSP Master Transmit Data Register (DTXM)

      160
    • 6.7.9 DSPSlaveTransmitData Register (DTXS)

      160
    • 6.7.10 DSP Host Port GPIO Direction Register (DIRH)

      161
    • 6.7.11 DSP Host Port GPIO Data Register (DATH)

      161
  • 6.8 Host-Side Programming Model

    162
    • 6.8.1 HI32 Control Register (HCTR)

      166
    • 6.8.2 Host Interface Status Register (HSTR)

      174
    • 6.8.3 Host Command Vector Register (HCVR)

      177
    • 6.8.4 Host Master Receive Data Register (HRXM)

      179
    • 6.8.5 Host Slave Receive Data Register (HRXS)

      179
    • 6.8.6 Host Transmit Data Register (HTXR)

      180
      • 6.8.6.1 PCI Mode (DCTR[HM] = $1)

        181
      • 6.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3)

        181
    • 6.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)

      182
    • 6.8.8 Status/Command Configuration Register (CSTR/CCMR)

      182
    • 6.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)

      185
    • 6.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)

      186
    • 6.8.11 Memory Space Base Address Configuration Register (CBMA)

      188
    • 6.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)

      189
    • 6.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP)

      191
  • 6.9 HI32 Programming Model/Quick Reference

    192
• Chapter7 Enhanced Synchronous Serial Interface (ESSI)

  199
  • 7.1 ESSI Enhancements

    200
  • 7.2 ESSI Data and Control Signals

    201
    • 7.2.1 Serial Transmit Data Signal (STD)

      201
    • 7.2.2 Serial Receive Data Signal (SRD)

      201
    • 7.2.3 Serial Clock (SCK)

      201
    • 7.2.4 Serial Control Signal (SC0)

      202
    • 7.2.5 Serial Control Signal (SC1)

      202
    • 7.2.6 Serial Control Signal (SC2)

      204
  • 7.3 Operation

    204
    • 7.3.1 ESSI After Reset

      204
    • 7.3.2 Initialization

      204
    • 7.3.3 Exceptions

      205
  • 7.4 Operating Modes: Normal, Network, and On-Demand

    208
    • 7.4.1 Normal/Network/On-Demand Mode Selection

      208
    • 7.4.2 Synchronous/Asynchronous Operating Modes

      209
    • 7.4.3 Frame Sync Selection

      209
    • 7.4.4 Frame Sync Signal Format

      209
    • 7.4.5 Frame Sync Length for Multiple Devices

      210
    • 7.4.6 Word Length Frame Sync and Data Word Timing

      210
    • 7.4.7 Frame Sync Polarity

      210
    • 7.4.8 Byte Format (LSB/MSB) for the Transmitter

      211
    • 7.4.9 Flags

      211
  • 7.5 ESSI Programming Model

    212
    • 7.5.1 ESSI Control Register A (CRA)

      212
    • 7.5.2 ESSI Control Register B (CRB)

      216
    • 7.5.3 ESSI Status Register (SSISR)

      226
    • 7.5.4 ESSI Receive Shift Register

      227
    • 7.5.5 ESSI Receive Data Register (RX)

      228
    • 7.5.6 ESSI Transmit Shift Registers

      228
    • 7.5.7 ESSI Transmit Data Registers (TX[2–0])

      231
    • 7.5.8 ESSI Time Slot Register (TSR)

      231
    • 7.5.9 Transmit Slot Mask Registers (TSMA, TSMB)

      231
    • 7.5.10 Receive Slot Mask Registers (RSMA, RSMB)

      233
  • 7.6 GPIO Signals and Registers

    234
    • 7.6.1 Port Control Registers (PCRC and PCRD)

      234
    • 7.6.2 Port Direction Registers (PRRC and PRRD)

      235
    • 7.6.3 Port Data Registers (PDRC and PDRD)

      236
• Chapter8 Serial Communication Interface (SCI)

  237
  • 8.1 Operating Modes

    237
    • 8.1.1 Synchronous Mode

      238
    • 8.1.2 Asynchronous Mode

      238
    • 8.1.3 Multidrop Mode

      238
      • 8.1.3.1 Transmitting Data and Address Characters

        239
      • 8.1.3.2 Wired-OR Mode

        239
      • 8.1.3.3 Idle Line Wakeup

        239
      • 8.1.3.4 Address Mode Wakeup

        239
  • 8.2 I/O Signals

    239
    • 8.2.1 Receive Data (RXD)

      240
    • 8.2.2 Transmit Data (TXD)

      240
    • 8.2.3 SCI Serial Clock (SCLK)

      240
  • 8.3 SCI After Reset

    241
  • 8.4 SCI Initialization

    242
    • 8.4.1 Preamble, Break, and Data Transmission Priority

      243
    • 8.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)

      244
  • 8.5 Exceptions

    244
  • 8.6 SCI Programming Model

    245
    • 8.6.1 SCI Control Register (SCR)

      248
    • 8.6.2 SCI Status Register (SSR)

      253
    • 8.6.3 SCI Clock Control Register (SCCR)

      255
    • 8.6.4 SCI Data Registers

      258
      • 8.6.4.1 SCI Receive Register (SRX)

        258
      • 8.6.4.2 SCI Transmit Register (STX)

        259
  • 8.7 GPIO Signals and Registers

    260
    • 8.7.1 Port E Control Register (PCRE)

      260
    • 8.7.2 Port E Direction Register (PRRE)

      261
    • 8.7.3 Port E Data Register (PDRE)

      261
• Chapter9 Triple Timer Module

  263
  • 9.1 Overview

    263
    • 9.1.1 Triple Timer Module Block Diagram

      264
    • 9.1.2 Individual Timer Block Diagram

      264
  • 9.2 Operation

    265
    • 9.2.1 Timer After Reset

      265
    • 9.2.2 Timer Initialization

      266
    • 9.2.3 Timer Exceptions

      266
  • 9.3 Operating Modes

    267
    • 9.3.1 Triple Timer Modes

      268
      • 9.3.1.1 Timer GPIO (Mode 0)

        268
      • 9.3.1.2 Timer Pulse (Mode 1)

        270
      • 9.3.1.3 Timer Toggle (Mode 2)

        272
      • 9.3.1.4 Timer Event Counter (Mode 3)

        274
    • 9.3.2 Signal Measurement Modes

      276
      • 9.3.2.1 Measurement Input Width (Mode 4)

        276
      • 9.3.2.2 Measurement Input Period (Mode 5)

        278
      • 9.3.2.3 Measurement Capture (Mode 6)

        280
    • 9.3.3 Pulse Width Modulation (PWM, Mode 7)

      281
    • 9.3.4 Watchdog Modes

      284
      • 9.3.4.1 Watchdog Pulse (Mode 9)

        284
      • 9.3.4.2 Watchdog Toggle (Mode 10)

        286
      • 9.3.4.3 Reserved Modes

        287
    • 9.3.5 Special Cases

      287
    • 9.3.6 DMA Trigger

      287
  • 9.4 Triple Timer Module Programming Model

    287
    • 9.4.1 Prescaler Counter

      287
    • 9.4.2 Timer Prescaler Load Register (TPLR)

      289
    • 9.4.3 Timer Prescaler Count Register (TPCR)

      290
    • 9.4.4 Timer Control/Status Register (TCSR)

      290
    • 9.4.5 Timer Load Register (TLR)

      295
    • 9.4.6 Timer Compare Register (TCPR)

      296
    • 9.4.7 Timer Count Register (TCR)

      296
• AppendixA Bootstrap Program

  297
• ChapterB Programming Reference

  313
  • B.1 Internal I/O Memory Map

    315
  • B.2 Interrupt Sources and Priorities

    321
  • B.3 Programming Sheets

    325
• Index

  357
  • A

    357
  • B

    357
  • C

    358
  • D

    358
  • E

    360
  • F

    361
  • G

    362
  • H

    362
  • I

    365
  • J

    365
  • L

    365
  • M

    365
  • N

    366
  • O

    366
  • P

    366
  • R

    367
  • S

    368
  • T

    370
  • U

    371
  • V

    371
  • W

    371
  • X

    371
  • Y

    372
  • Z

    372