ユーザーズマニュアル目次Title Page1Contents5Figures11Tables15Chapter1 Overview171.1 Manual Organization171.2 Manual Conventions181.3 DSP56300 Core Features201.4 DSP56300 Core Functional Blocks221.4.1 Data ALU221.4.1.1 Data ALU Registers231.4.1.2 Multiplier-Accumulator (MAC)231.4.2 Address Generation Unit (AGU)231.4.3 Program Control Unit (PCU)241.4.4 PLL and Clock Oscillator251.4.5 JTAG TAP and OnCE Module251.4.6 On-Chip Memory261.5 Internal Buses261.6 DMA271.7 Peripherals281.7.1 General-Purpose Input/Output (GPIO) signals281.7.2 Host Interface (HI32)281.7.3 Enhance Synchronous Serial Interface (ESSI)281.7.4 Serial Communications Interface (SCI)291.7.5 Triple Timer Module291.8 Related Documents and Web Sites30Chapter2 Signals/Connections312.1 Power342.2 Ground342.3 Clock352.4 PLL352.5 External Memory Expansion Port (Port A)362.5.1 External Address Bus362.5.2 External Data Bus362.5.3 External Bus Control362.6 Interrupt and Mode Control392.7 Host Interface (HI32)402.8 Enhanced Synchronous Serial Interface 0522.9 Enhanced Synchronous Serial Interface 1552.10 Serial Communications Interface (SCI)572.11 Timers572.12 JTAG and OnCE Interface59Chapter3 Memory Configuration613.1 Program Memory Space613.1.1 Internal Program Memory623.1.2 Memory Switch Modes—Program Memory623.1.3 Instruction Cache623.1.4 Program Bootstrap ROM633.2 X Data Memory Space633.2.1 Internal X Data Memory633.2.2 Memory Switch Modes—X Data Memory633.2.3 Internal I/O Space—X Data Memory643.3 Y Data Memory Space643.3.1 Internal Y Data Memory643.3.2 Memory Switch Modes—Y Data Memory643.3.3 External I/O Space—Y Data Memory653.4 Dynamic Memory Configuration Switching653.5 Sixteen-Bit Compatibility Mode Configuration663.6 Internal Memory Configuration Summary663.7 Memory Maps67Chapter4 Core Configuration754.1 Operating Modes764.2 Bootstrap Program794.3 Central Processor Unit (CPU) Registers804.3.1 Status Register (SR)804.3.2 Operating Mode Register (OMR)864.4 Configuring Interrupts894.4.1 Interrupt Priority Registers (IPRC and IPRP)904.4.2 Interrupt Table Memory Map914.4.3 Processing Interrupt Source Priorities Within an IPL934.5 PLL Control Register (PCTL)954.6 Bus Interface Unit (BIU) Registers964.6.1 Bus Control Register964.6.2 DRAM Control Register (DCR)984.6.3 Address Attribute Registers (AAR[0–3])1014.7 DMA Control Registers 5–0 (DCR[5–0])1034.8 Device Identification Register (IDR)1084.9 JTAG Identification (ID) Register1094.10 JTAG Boundary Scan Register (BSR)109Chapter5 Programming the Peripherals1115.1 Peripheral Initialization Steps1115.2 Mapping the Control Registers1125.3 Data Transfer Methods1125.3.1 Polling1125.3.2 Interrupts1135.3.3 DMA1145.3.4 Advantages and Disadvantages1145.4 General-Purpose Input/Output (GPIO)1145.4.1 Port B Signals and Registers1155.4.2 Port C Signals and Registers1165.4.3 Port D Signals and Registers1165.4.4 Port E Signals and Registers1165.4.5 Triple Timer Signals and Registers117Chapter6 Host Interface (HI32)1196.1 Features1196.2 Overview1226.3 Data Transfer Paths1246.3.1 Host-to-DSP Data Path1246.3.2 DSP-To-Host Data Path1256.4 Reset States1306.5 DSP-Side Operating Modes1306.5.1 Terminate and Reset (DCTR[HM] = $0)1316.5.2 PCI Mode (DCTR[HM] = $1)1316.5.3 Universal (DCTR[HM] = $2) and Enhanced Universal (DCTR[HM] = $3) Bus Modes1336.5.4 GPIO Mode (DCTR[HM] = $4)1346.5.5 Self-Configuration Mode (DCTR[HM] = $5)1346.6 Host Port Pins1366.7 HI32 DSP-Side Programming Model1406.7.1 DSP Control Register (DCTR)1416.7.2 DSP PCI Control Register (DPCR)1446.7.3 DSP PCI Master Control Register (DPMC)1486.7.4 DSP PCI Address Register (DPAR)1516.7.5 DSP Status Register (DSR)1536.7.6 DSP PCI Status Register (DPSR)1566.7.7 DSP Receive Data FIFO (DRXR)1596.7.8 DSP Master Transmit Data Register (DTXM)1606.7.9 DSPSlaveTransmitData Register (DTXS)1606.7.10 DSP Host Port GPIO Direction Register (DIRH)1616.7.11 DSP Host Port GPIO Data Register (DATH)1616.8 Host-Side Programming Model1626.8.1 HI32 Control Register (HCTR)1666.8.2 Host Interface Status Register (HSTR)1746.8.3 Host Command Vector Register (HCVR)1776.8.4 Host Master Receive Data Register (HRXM)1796.8.5 Host Slave Receive Data Register (HRXS)1796.8.6 Host Transmit Data Register (HTXR)1806.8.6.1 PCI Mode (DCTR[HM] = $1)1816.8.6.2 Universal Bus mode (DCTR[HM] = $2 or $3)1816.8.7 Device ID/Vendor ID Configuration Register (CDID/CVID)1826.8.8 Status/Command Configuration Register (CSTR/CCMR)1826.8.9 Class Code/Revision ID Configuration Register (CCCR/CRID)1856.8.10 Header Type/Latency Timer Configuration Register (CHTY/CLAT/CCLS)1866.8.11 Memory Space Base Address Configuration Register (CBMA)1886.8.12 Subsystem ID and Subsystem Vendor ID Configuration Register (CSID)1896.8.13 Interrupt Line-Interrupt Pin Configuration Register(CILP)1916.9 HI32 Programming Model/Quick Reference192Chapter7 Enhanced Synchronous Serial Interface (ESSI)1997.1 ESSI Enhancements2007.2 ESSI Data and Control Signals2017.2.1 Serial Transmit Data Signal (STD)2017.2.2 Serial Receive Data Signal (SRD)2017.2.3 Serial Clock (SCK)2017.2.4 Serial Control Signal (SC0)2027.2.5 Serial Control Signal (SC1)2027.2.6 Serial Control Signal (SC2)2047.3 Operation2047.3.1 ESSI After Reset2047.3.2 Initialization2047.3.3 Exceptions2057.4 Operating Modes: Normal, Network, and On-Demand2087.4.1 Normal/Network/On-Demand Mode Selection2087.4.2 Synchronous/Asynchronous Operating Modes2097.4.3 Frame Sync Selection2097.4.4 Frame Sync Signal Format2097.4.5 Frame Sync Length for Multiple Devices2107.4.6 Word Length Frame Sync and Data Word Timing2107.4.7 Frame Sync Polarity2107.4.8 Byte Format (LSB/MSB) for the Transmitter2117.4.9 Flags2117.5 ESSI Programming Model2127.5.1 ESSI Control Register A (CRA)2127.5.2 ESSI Control Register B (CRB)2167.5.3 ESSI Status Register (SSISR)2267.5.4 ESSI Receive Shift Register2277.5.5 ESSI Receive Data Register (RX)2287.5.6 ESSI Transmit Shift Registers2287.5.7 ESSI Transmit Data Registers (TX[2–0])2317.5.8 ESSI Time Slot Register (TSR)2317.5.9 Transmit Slot Mask Registers (TSMA, TSMB)2317.5.10 Receive Slot Mask Registers (RSMA, RSMB)2337.6 GPIO Signals and Registers2347.6.1 Port Control Registers (PCRC and PCRD)2347.6.2 Port Direction Registers (PRRC and PRRD)2357.6.3 Port Data Registers (PDRC and PDRD)236Chapter8 Serial Communication Interface (SCI)2378.1 Operating Modes2378.1.1 Synchronous Mode2388.1.2 Asynchronous Mode2388.1.3 Multidrop Mode2388.1.3.1 Transmitting Data and Address Characters2398.1.3.2 Wired-OR Mode2398.1.3.3 Idle Line Wakeup2398.1.3.4 Address Mode Wakeup2398.2 I/O Signals2398.2.1 Receive Data (RXD)2408.2.2 Transmit Data (TXD)2408.2.3 SCI Serial Clock (SCLK)2408.3 SCI After Reset2418.4 SCI Initialization2428.4.1 Preamble, Break, and Data Transmission Priority2438.4.2 Bootstrap Loading Through the SCI (Boot Mode 2 or A)2448.5 Exceptions2448.6 SCI Programming Model2458.6.1 SCI Control Register (SCR)2488.6.2 SCI Status Register (SSR)2538.6.3 SCI Clock Control Register (SCCR)2558.6.4 SCI Data Registers2588.6.4.1 SCI Receive Register (SRX)2588.6.4.2 SCI Transmit Register (STX)2598.7 GPIO Signals and Registers2608.7.1 Port E Control Register (PCRE)2608.7.2 Port E Direction Register (PRRE)2618.7.3 Port E Data Register (PDRE)261Chapter9 Triple Timer Module2639.1 Overview2639.1.1 Triple Timer Module Block Diagram2649.1.2 Individual Timer Block Diagram2649.2 Operation2659.2.1 Timer After Reset2659.2.2 Timer Initialization2669.2.3 Timer Exceptions2669.3 Operating Modes2679.3.1 Triple Timer Modes2689.3.1.1 Timer GPIO (Mode 0)2689.3.1.2 Timer Pulse (Mode 1)2709.3.1.3 Timer Toggle (Mode 2)2729.3.1.4 Timer Event Counter (Mode 3)2749.3.2 Signal Measurement Modes2769.3.2.1 Measurement Input Width (Mode 4)2769.3.2.2 Measurement Input Period (Mode 5)2789.3.2.3 Measurement Capture (Mode 6)2809.3.3 Pulse Width Modulation (PWM, Mode 7)2819.3.4 Watchdog Modes2849.3.4.1 Watchdog Pulse (Mode 9)2849.3.4.2 Watchdog Toggle (Mode 10)2869.3.4.3 Reserved Modes2879.3.5 Special Cases2879.3.6 DMA Trigger2879.4 Triple Timer Module Programming Model2879.4.1 Prescaler Counter2879.4.2 Timer Prescaler Load Register (TPLR)2899.4.3 Timer Prescaler Count Register (TPCR)2909.4.4 Timer Control/Status Register (TCSR)2909.4.5 Timer Load Register (TLR)2959.4.6 Timer Compare Register (TCPR)2969.4.7 Timer Count Register (TCR)296AppendixA Bootstrap Program297ChapterB Programming Reference313B.1 Internal I/O Memory Map315B.2 Interrupt Sources and Priorities321B.3 Programming Sheets325Index357A357B357C358D358E360F361G362H362I365J365L365M365N366O366P366R367S368T370U371V371W371X371Y372Z372サイズ: 4.88MBページ数: 372Language: Englishマニュアルを開く