Manuais de utilizador para SDI Technologies SDIO Card

índice analítico

• 7

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• 1. General Description

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• SDIO Features

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• Primary Reference Document

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• Standard SDIO Functions

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• 2. SDIO Signaling Definition

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• SDIO Card Types

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• SDIO Card modes

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• SPI (Card mandatory support)

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• 1-bit SD Data Transfer Mode (Card Mandatory Support)

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• 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed)

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• SDIO Host Modes

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• Signal Pins

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• Figure 2-1 Signal connection to two 4-bit SDIO cards

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• 3. SDIO Card Initialization

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• Differences in I/O card Initialization

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• Figure 3-1 SDIO response to non-I/O aware initialization

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• Figure 3-2 Card initialization flow in SD mode (SDIO aware host)

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• Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)

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• The IO_SEND_OP_COND Command (CMD5)

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• Table 3-1 OCR Values for CMD5

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• Figure 3-4 IO_SEND_OP_COND Command (CMD5)

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• The IO_SEND_OP_COND Response (R4)

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• Figure 3-5 Response R4 in SD mode

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• Figure 3-6 Response R4 in SPI mode

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• Figure 3-7 Modified R1 Response

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• Special Initialization considerations for Combo Cards

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• Re-initialize both I/O and Memory

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• Using a Combo Card as SDIO only or SD Memory only after Combo Initialization

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• Acceptable Commands after Initialization

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• Recommendations for RCA after Reset

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• Figure 3-8 Re-Initialization Flow for I/O Controller

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• Figure 3-9 Re-Initialization Flow for Memory controller

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• Enabling CRC in SPI Combo Card

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• 4. Differences with SD Memory Specification

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• SDIO Command List

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• Unsupported SD Memory Commands

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• Modified R6 Response

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• Reset for SDIO

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• Bus Width

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• Table 4-1 Unsupported SD Memory Commands

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• Table 4-2 R6 response to CMD3

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• Table 4-3 SDIO R6 Status Bits

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• Card Detect Resistor

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• Timings

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• Table 4-4 Combo Card 4-bit Control

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• Table 4-5 Card Detect Resistor States

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• Table 4-6 is blanked

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• Data Transfer Block Sizes

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• Data Transfer Abort

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• Read Abort

  18
• Write Abort

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• 4.10.1 OCR Register

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• 4.10.2 CID Register

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• 4.10.3 CSD Register

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• 4.10.4 RCA Register

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• 4.10.5 DSR Register

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• 4.10.6 SCR Register

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• 4.10.7 SD Status

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• 4.10.8 Card Status Register

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• Table 4-7 SDIO Status Register Structure

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• 5. New I/O Read/Write Commands

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• IO_RW_DIRECT Command (CMD52)

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• Figure 5-1 IO_RW_DIRECT Command

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• IO_RW_DIRECT Response (R5)

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• CMD52 Response (SD modes)

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• Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)

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• R5, IO_RW_DIRECT Response (SPI mode)

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• Table 5-1 Flag data for IO_RW_DIRECT SD Response

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• Figure 5-3 IO_RW_DIRECT Response in SPI Mode

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• IO_RW_EXTENDED Command (CMD53)

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• Table 5-2 IO_RW_ EXTENDED command Op Code Definition

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• Figure 5-4 IO_RW_EXTENDED Command

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• CMD53 Data Transfer Format

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• Special Timing for CMD53 Multi-Block Read

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• Table 5-3 Byte Count Values

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• 6. SDIO Card Internal Operation

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• Overview

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• Register Access Time

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• Interrupts

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• Suspend/Resume

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• Read Wait

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• CMD52 During Data Transfer

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• SDIO Fixed Internal Map

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• Common I/O Area (CIA)

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• Card Common Control Registers (CCCR)

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• Figure 6-1 SDIO Internal Map

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• Table 6-1 Card Common Control Registers (CCCR)

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• Table 6-2 CCCR bit Definitions

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• Table 6-3 Function Basic Information Registers (FBR)

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• Table 6-4 FBR bit and field definitions

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• 6.11 Card Information Structure (CIS)

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• 6.13 Setting Block Size with CMD53

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• Table 6-5 Card Information Structure (CIS) and reserved area of CIA

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• Figure 6-2 State Diagram for Bus State Machine

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• 7. Embedded I/O Code Storage Area (CSA)

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• CSA Access

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• CSA Data Format

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• 8. SDIO Interrupts

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• Interrupt Timing

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• SPI and SD 1-bit Mode Interrupts

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• SD 4-bit Mode

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• Interrupt Period Definition

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• Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)

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• Inhibited Interrupts (Removed Section)

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• End of Interrupt Cycles

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• Terminated Data Transfer Interrupt Cycle

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• Interrupt Clear Timing

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• 9. SDIO Suspend/Resume Operation

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• 10. SDIO Read Wait Operation

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• 11. Power Control

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• 11.2 Power Control support for SDIO Cards

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• 11.2.1 Master Power Control

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• 11.2.2 Power Selection

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• 11.2.3 High-Power Tuples

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• 11.3.1 Version 1.10 Host

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• Table 11-1 Reference Tuples by Master Power Control and Power Select

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• 11.3.2 Power Control Operation

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• 12. High-Speed Mode

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• 12.2 Switching Bus Speed Mode in a Combo Card

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• 13. SDIO Physical Properties

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• 13.2 Full-Size SDIO

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• 14. SDIO Power

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• 14.2 SDIO Power Consumption

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• 15. Inrush Current Limiting

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• 16. CIS Formats

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• 16.2 Basic Tuple Format and Tuple Chain Structure

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• Table 16-1 Basic Tuple Format

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• 16.4 Tuple Version

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• Table 16-2 Tuples Supported by SDIO Cards

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• 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple

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• 16.7.1 CISTPL_FUNCID: Function Identification Tuple

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• Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple

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• Table 16-4 CISTPL_FUNCID Tuple

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• 16.7.2 CISTPL_FUNCE: Function Extension Tuple

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• 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common)

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• Table 16-5 CISTPL_FUNCE Tuple General Structure

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• Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)

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• Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common)

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• 16.7.4 CISTPL_FUNCE Tuple for Function 1-7

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• Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7

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• Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7

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• Table 16-10 TPLFE_FUNCTION_INFO Definition

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• Table 16-11 TPLFE_CSA_PROPERTY Definition

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• 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function

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• 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards

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• Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards

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• Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards

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• Appendix A

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• Table A-14 SD Mode Command List

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• Table A-15 SPI Mode Command List

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• Appendix B

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• Appendix C

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• Appendix D

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